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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00004## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00005##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00006## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Patrick Georgi0588d192009-08-12 15:00:51 +000018##
19
20mainmenu "Coreboot Configuration"
21
Uwe Hermannc04be932009-10-05 13:55:28 +000022menu "General setup"
23
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000024config EXPERT
25 bool "Expert mode"
26 help
27 This allows you to select certain advanced configuration options.
28
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
31
Uwe Hermannc04be932009-10-05 13:55:28 +000032config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000033 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000034 help
35 Append an extra string to the end of the coreboot version.
36
Uwe Hermann168b11b2009-10-07 16:15:40 +000037 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
41
Patrick Georgi4b8a2412010-02-09 19:35:16 +000042config CBFS_PREFIX
43 string "CBFS prefix to use"
44 default "fallback"
45 help
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
48
Patrick Georgi23d89cc2010-03-16 01:17:19 +000049choice
50 prompt "Compiler"
51 default COMPILER_GCC
52 help
53 This option allows you to select the compiler used for building
54 coreboot.
55
56config COMPILER_GCC
57 bool "GCC"
58config COMPILER_LLVM_CLANG
59 bool "LLVM/clang"
60endchoice
61
Patrick Georgi020f51f2010-03-14 21:25:03 +000062config SCANBUILD_ENABLE
Patrick Georgi23d89cc2010-03-16 01:17:19 +000063 bool "Build with scan-build for static analysis"
Patrick Georgi020f51f2010-03-14 21:25:03 +000064 default n
65 help
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
68
69config SCANBUILD_REPORT_LOCATION
Patrick Georgi23d89cc2010-03-16 01:17:19 +000070 string "Directory to put scan-build report in"
Patrick Georgi020f51f2010-03-14 21:25:03 +000071 default ""
72 depends on SCANBUILD_ENABLE
73 help
74 Where the scan-build report should be stored
75
Patrick Georgi516a2a72010-03-25 21:45:25 +000076config CCACHE
77 bool "ccache"
78 default n
79 help
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
82
Joe Korty6d772522010-05-19 18:41:15 +000083config USE_OPTION_TABLE
84 bool "Use CMOS for configuration values"
85 default n
Edwin Beasanteb50c7d2010-07-06 21:05:04 +000086 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +000087 help
88 Enable this option if coreboot shall read options from the "CMOS"
89 NVRAM instead of using hard coded values.
90
Uwe Hermannc04be932009-10-05 13:55:28 +000091endmenu
92
Patrick Georgi0588d192009-08-12 15:00:51 +000093source src/mainboard/Kconfig
94source src/arch/i386/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +000095
96menu "Chipset"
97
98comment "CPU"
Patrick Georgi0588d192009-08-12 15:00:51 +000099source src/cpu/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000100comment "Northbridge"
101source src/northbridge/Kconfig
102comment "Southbridge"
103source src/southbridge/Kconfig
104comment "Super I/O"
105source src/superio/Kconfig
106comment "Devices"
107source src/devices/Kconfig
108
109endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000110
Rudolf Marekd9c25492010-05-16 15:31:53 +0000111menu "Generic Drivers"
112source src/drivers/Kconfig
113endmenu
114
Patrick Georgi0588d192009-08-12 15:00:51 +0000115config PCI_BUS_SEGN_BITS
Myles Watson74fb8f22009-09-24 15:09:11 +0000116 int
117 default 0
Patrick Georgi892b0912009-09-24 09:03:06 +0000118
Patrick Georgi0588d192009-08-12 15:00:51 +0000119config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000120 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000121 default 0x0
Patrick Georgi0588d192009-08-12 15:00:51 +0000122
123config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000124 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000125 default 0x0
Patrick Georgi0588d192009-08-12 15:00:51 +0000126
127config CPU_ADDR_BITS
128 int
129 default 36
130
Patrick Georgi0588d192009-08-12 15:00:51 +0000131config LOGICAL_CPUS
Myles Watson45bb25f2009-09-22 18:49:08 +0000132 bool
133 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000134
135config PCI_ROM_RUN
Patrick Georgi698c0e0e2009-08-25 17:38:24 +0000136 bool
137 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000138
Patrick Georgi0588d192009-08-12 15:00:51 +0000139config HEAP_SIZE
140 hex
Myles Watson04000f42009-10-16 19:12:49 +0000141 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000142
Patrick Georgi0588d192009-08-12 15:00:51 +0000143config MAX_CPUS
144 int
145 default 1
146
147config MMCONF_SUPPORT_DEFAULT
148 bool
149 default n
150
151config MMCONF_SUPPORT
152 bool
153 default n
154
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000155config ATI_RAGE_XL
156 bool
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000157
Patrick Georgi0588d192009-08-12 15:00:51 +0000158source src/console/Kconfig
159
160config HAVE_ACPI_RESUME
161 bool
162 default n
163
Stefan Reinauerc4f1a772010-06-05 10:03:08 +0000164config HAVE_ACPI_SLIC
165 bool
166 default n
167
Patrick Georgi0588d192009-08-12 15:00:51 +0000168config ACPI_SSDTX_NUM
169 int
170 default 0
171
Patrick Georgi0588d192009-08-12 15:00:51 +0000172config HAVE_HARD_RESET
173 bool
Patrick Georgi37bdb872010-02-27 08:39:04 +0000174 default y if BOARD_HAS_HARD_RESET
Uwe Hermann748475b2009-10-09 11:47:21 +0000175 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000176 help
177 This variable specifies whether a given board has a hard_reset
178 function, no matter if it's provided by board code or chipset code.
179
Patrick Georgi0588d192009-08-12 15:00:51 +0000180config HAVE_INIT_TIMER
181 bool
Patrick Georgi1f807fd2010-01-04 20:09:27 +0000182 default n if UDELAY_IO
Myles Watsond73c1b52009-10-26 15:14:07 +0000183 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000184
185config HAVE_MAINBOARD_RESOURCES
186 bool
187 default n
188
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000189config USE_OPTION_TABLE
190 bool
191 default n
192
Patrick Georgi0588d192009-08-12 15:00:51 +0000193config HAVE_OPTION_TABLE
194 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000195 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000196 help
197 This variable specifies whether a given board has a cmos.layout
198 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000199 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000200
Patrick Georgi0588d192009-08-12 15:00:51 +0000201config PIRQ_ROUTE
202 bool
203 default n
204
205config HAVE_SMI_HANDLER
206 bool
207 default n
208
209config PCI_IO_CFG_EXT
210 bool
211 default n
212
213config IOAPIC
214 bool
215 default n
216
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000217# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000218config VIDEO_MB
219 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000220 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000221
Myles Watson45bb25f2009-09-22 18:49:08 +0000222config USE_WATCHDOG_ON_BOOT
223 bool
224 default n
225
226config VGA
227 bool
228 default n
229 help
230 Build board-specific VGA code.
231
232config GFXUMA
233 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000234 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000235 help
236 Enable Unified Memory Architecture for graphics.
237
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000238# TODO
239# menu "Drivers"
Uwe Hermann168b11b2009-10-07 16:15:40 +0000240#
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000241# endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000242
Myles Watsond73c1b52009-10-26 15:14:07 +0000243#TODO Remove this option or make it useful.
244config HAVE_LOW_TABLES
245 bool
246 default y
247 help
248 This Option is unused in the code. Since two boards try to set it to
249 'n', they may be broken. We either need to make the option useful or
250 get rid of it. The broken boards are:
251 asus/m2v-mx_se
252 supermicro/h8dme
253
254config HAVE_HIGH_TABLES
255 bool
Stefan Reinauer13f2bb02010-02-25 13:45:08 +0000256 default y
Myles Watsond73c1b52009-10-26 15:14:07 +0000257 help
258 This variable specifies whether a given northbridge has high table
259 support.
260 It is set in northbridge/*/Kconfig.
261 Whether or not the high tables are actually written by coreboot is
262 configurable by the user via WRITE_HIGH_TABLES.
263
Myles Watsonb8e20272009-10-15 13:35:47 +0000264config HAVE_ACPI_TABLES
265 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000266 help
267 This variable specifies whether a given board has ACPI table support.
268 It is usually set in mainboard/*/Kconfig.
269 Whether or not the ACPI tables are actually generated by coreboot
270 is configurable by the user via GENERATE_ACPI_TABLES.
Myles Watsonb8e20272009-10-15 13:35:47 +0000271
272config HAVE_MP_TABLE
273 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000274 help
275 This variable specifies whether a given board has MP table support.
276 It is usually set in mainboard/*/Kconfig.
277 Whether or not the MP table is actually generated by coreboot
278 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000279
280config HAVE_PIRQ_TABLE
281 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000282 help
283 This variable specifies whether a given board has PIRQ table support.
284 It is usually set in mainboard/*/Kconfig.
285 Whether or not the PIRQ table is actually generated by coreboot
286 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000287
Myles Watsond73c1b52009-10-26 15:14:07 +0000288#These Options are here to avoid "undefined" warnings.
289#The actual selection and help texts are in the following menu.
290
291config GENERATE_ACPI_TABLES
Myles Watsonb8e20272009-10-15 13:35:47 +0000292 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000293 default HAVE_ACPI_TABLES
294
295config GENERATE_MP_TABLE
296 bool
297 default HAVE_MP_TABLE
298
299config GENERATE_PIRQ_TABLE
300 bool
301 default HAVE_PIRQ_TABLE
302
303config WRITE_HIGH_TABLES
304 bool
305 default HAVE_HIGH_TABLES
Myles Watsonb8e20272009-10-15 13:35:47 +0000306
Uwe Hermann168b11b2009-10-07 16:15:40 +0000307menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000308
Myles Watsonb8e20272009-10-15 13:35:47 +0000309config WRITE_HIGH_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000310 bool "Write 'high' tables to avoid being overwritten in F segment"
Myles Watsonb8e20272009-10-15 13:35:47 +0000311 depends on HAVE_HIGH_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000312 default y
313
314config MULTIBOOT
Uwe Hermann168b11b2009-10-07 16:15:40 +0000315 bool "Generate Multiboot tables (for GRUB2)"
Ronald G. Minnich7f91d922009-11-09 17:56:47 +0000316 default y
Myles Watson45bb25f2009-09-22 18:49:08 +0000317
Myles Watsonb8e20272009-10-15 13:35:47 +0000318config GENERATE_ACPI_TABLES
319 depends on HAVE_ACPI_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000320 bool "Generate ACPI tables"
Myles Watsonb8e20272009-10-15 13:35:47 +0000321 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000322 help
323 Generate ACPI tables for this board.
324
325 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000326
Myles Watsonb8e20272009-10-15 13:35:47 +0000327config GENERATE_MP_TABLE
328 depends on HAVE_MP_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000329 bool "Generate an MP table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000330 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000331 help
332 Generate an MP table (conforming to the Intel MultiProcessor
333 specification 1.4) for this board.
334
335 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000336
Myles Watsonb8e20272009-10-15 13:35:47 +0000337config GENERATE_PIRQ_TABLE
338 depends on HAVE_PIRQ_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000339 bool "Generate a PIRQ table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000340 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000341 help
342 Generate a PIRQ table for this board.
343
344 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000345
346endmenu
347
Patrick Georgi0588d192009-08-12 15:00:51 +0000348menu "Payload"
349
Patrick Georgi0588d192009-08-12 15:00:51 +0000350choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000351 prompt "Add a payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000352 default PAYLOAD_NONE
353
Uwe Hermann168b11b2009-10-07 16:15:40 +0000354config PAYLOAD_NONE
355 bool "None"
356 help
357 Select this option if you want to create an "empty" coreboot
358 ROM image for a certain mainboard, i.e. a coreboot ROM image
359 which does not yet contain a payload.
360
361 For such an image to be useful, you have to use 'cbfstool'
362 to add a payload to the ROM image later.
363
Patrick Georgi0588d192009-08-12 15:00:51 +0000364config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000365 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000366 help
367 Select this option if you have a payload image (an ELF file)
368 which coreboot should run as soon as the basic hardware
369 initialization is completed.
370
371 You will be able to specify the location and file name of the
372 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000373
374endchoice
375
Patrick Georgi0588d192009-08-12 15:00:51 +0000376config FALLBACK_PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000377 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000378 depends on PAYLOAD_ELF
379 default "payload.elf"
380 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000381 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000382
Uwe Hermann168b11b2009-10-07 16:15:40 +0000383# TODO: Defined if no payload? Breaks build?
384config COMPRESSED_PAYLOAD_LZMA
385 bool "Use LZMA compression for payloads"
386 default y
387 depends on PAYLOAD_ELF
388 help
389 In order to reduce the size payloads take up in the ROM chip
390 coreboot can compress them using the LZMA algorithm.
391
Myles Watson04000f42009-10-16 19:12:49 +0000392config COMPRESSED_PAYLOAD_NRV2B
Peter Stuged7b37b02009-10-17 03:00:04 +0000393 bool
Myles Watson04000f42009-10-16 19:12:49 +0000394 default n
395
Peter Stugea758ca22009-09-17 16:21:31 +0000396endmenu
397
398menu "VGA BIOS"
399
400config VGA_BIOS
401 bool "Add a VGA BIOS image"
402 help
403 Select this option if you have a VGA BIOS image that you would
404 like to add to your ROM.
405
406 You will be able to specify the location and file name of the
407 image later.
408
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000409config FALLBACK_VGA_BIOS_FILE
410 string "VGA BIOS path and filename"
411 depends on VGA_BIOS
412 default "vgabios.bin"
413 help
414 The path and filename of the file to use as VGA BIOS.
415
416config FALLBACK_VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +0000417 string "VGA device PCI IDs"
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000418 depends on VGA_BIOS
419 default "1106,3230"
420 help
Uwe Hermann168b11b2009-10-07 16:15:40 +0000421 The comma-separated PCI vendor and device ID that would associate
422 your VGA BIOS to your video card.
423
424 Example: 1106,3230
425
426 In the above example 1106 is the PCI vendor ID (in hex, but without
427 the "0x" prefix) and 3230 specifies the PCI device ID of the
428 video card (also in hex, without "0x" prefix).
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000429
Stefan Reinauer800379f2010-03-01 08:34:19 +0000430config INTEL_MBI
431 bool "Add an MBI image"
432 depends on NORTHBRIDGE_INTEL_I82830
433 help
434 Select this option if you have an Intel MBI image that you would
435 like to add to your ROM.
436
437 You will be able to specify the location and file name of the
438 image later.
439
440config FALLBACK_MBI_FILE
441 string "Intel MBI path and filename"
442 depends on INTEL_MBI
443 default "mbi.bin"
444 help
445 The path and filename of the file to use as VGA BIOS.
446
447endmenu
448
449menu "Bootsplash"
450 depends on PCI_OPTION_ROM_RUN_YABEL
451
452config BOOTSPLASH
453 prompt "Show graphical bootsplash"
454 bool
455 depends on PCI_OPTION_ROM_RUN_YABEL
456 help
457 This option shows a graphical bootsplash screen. The grapics are
458 loaded from the CBFS file bootsplash.jpg.
459
460config FALLBACK_BOOTSPLASH_FILE
461 string "Bootsplash path and filename"
462 depends on BOOTSPLASH
463 default "bootsplash.jpg"
464 help
Stefan Reinauer14e22772010-04-27 06:56:47 +0000465 The path and filename of the file to use as graphical bootsplash
466 screen. The file format has to be jpg.
Stefan Reinauer800379f2010-03-01 08:34:19 +0000467
468# TODO: Turn this into a "choice".
469config FRAMEBUFFER_VESA_MODE
470 prompt "VESA framebuffer video mode"
471 hex
472 default 0x117
473 depends on BOOTSPLASH
474 help
475 This option sets the resolution used for the coreboot framebuffer and
476 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
477 some day make this a "choice".
478
479config COREBOOT_KEEP_FRAMEBUFFER
480 prompt "Keep VESA framebuffer"
481 bool
482 depends on BOOTSPLASH
483 help
484 This option keeps the framebuffer mode set after coreboot finishes
485 execution. If this option is enabled, coreboot will pass a
486 framebuffer entry in its coreboot table and the payload will need a
487 framebuffer driver. If this option is disabled, coreboot will switch
488 back to text mode before handing control to a payload.
489
Patrick Georgi0588d192009-08-12 15:00:51 +0000490endmenu
491
Uwe Hermann168b11b2009-10-07 16:15:40 +0000492menu "Debugging"
493
494# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000495config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000496 bool "GDB debugging support"
Patrick Georgi0588d192009-08-12 15:00:51 +0000497 default y
498 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000499 If enabled, you will be able to set breakpoints for gdb debugging.
500 See src/arch/i386/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000501
Uwe Hermann01ce6012010-03-05 10:03:50 +0000502config DEBUG_RAM_SETUP
503 bool "Output verbose RAM init debug messages"
504 default n
505 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
506 || NORTHBRIDGE_AMD_AMDK8 \
507 || NORTHBRIDGE_VIA_CN700 \
508 || NORTHBRIDGE_VIA_CX700 \
509 || NORTHBRIDGE_VIA_VX800 \
510 || NORTHBRIDGE_INTEL_E7501 \
511 || NORTHBRIDGE_INTEL_I440BX \
512 || NORTHBRIDGE_INTEL_I82810 \
513 || NORTHBRIDGE_INTEL_I82830 \
514 || NORTHBRIDGE_INTEL_I945)
515 help
516 This option enables additional RAM init related debug messages.
517 It is recommended to enable this when debugging issues on your
518 board which might be RAM init related.
519
520 Note: This option will increase the size of the coreboot image.
521
522 If unsure, say N.
523
Myles Watson80e914ff2010-06-01 19:25:31 +0000524config DEBUG_PIRQ
525 bool "Check PIRQ table consistency"
526 default n
527 depends on GENERATE_PIRQ_TABLE
528 help
529 If unsure, say N.
530
Uwe Hermann01ce6012010-03-05 10:03:50 +0000531config DEBUG_SMBUS
532 bool "Output verbose SMBus debug messages"
533 default n
534 depends on (SOUTHBRIDGE_VIA_VT8237R \
535 || NORTHBRIDGE_VIA_VX800 \
536 || NORTHBRIDGE_VIA_CX700 \
Stefan Reinauer8f2c6162010-04-06 21:50:21 +0000537 || NORTHBRIDGE_AMD_AMDK8 \
Stefan Reinauer8a9268452010-04-07 03:40:37 +0000538 || NORTHBRIDGE_AMD_AMDFAM10 \
Myles Watson80e914ff2010-06-01 19:25:31 +0000539 || BOARD_LIPPERT_SPACERUNNER_LX \
Stefan Reinauer8a9268452010-04-07 03:40:37 +0000540 || SOUTHBRIDGE_VIA_VT8231)
Uwe Hermann01ce6012010-03-05 10:03:50 +0000541 help
542 This option enables additional SMBus (and SPD) debug messages.
543
544 Note: This option will increase the size of the coreboot image.
545
546 If unsure, say N.
547
548config DEBUG_SMI
549 bool "Output verbose SMI debug messages"
550 default n
551 depends on HAVE_SMI_HANDLER
552 help
553 This option enables additional SMI related debug messages.
554
555 Note: This option will increase the size of the coreboot image.
556
557 If unsure, say N.
558
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000559config DEBUG_SMM_RELOCATION
560 bool "Debug SMM relocation code"
561 default n
562 depends on HAVE_SMI_HANDLER
563 help
564 This option enables additional SMM handler relocation related
565 debug messages.
566
567 Note: This option will increase the size of the coreboot image.
568
569 If unsure, say N.
570
Uwe Hermann01ce6012010-03-05 10:03:50 +0000571config X86EMU_DEBUG
572 bool "Output verbose x86emu debug messages"
573 default n
574 depends on PCI_OPTION_ROM_RUN_YABEL
575 help
576 This option enables additional x86emu related debug messages.
577
578 Note: This option will increase the size of the coreboot image.
579
580 If unsure, say N.
581
582config X86EMU_DEBUG_JMP
583 bool "Trace JMP/RETF"
584 default n
585 depends on X86EMU_DEBUG
586 help
587 Print information about JMP and RETF opcodes from x86emu.
588
589 Note: This option will increase the size of the coreboot image.
590
591 If unsure, say N.
592
593config X86EMU_DEBUG_TRACE
594 bool "Trace all opcodes"
595 default n
596 depends on X86EMU_DEBUG
597 help
598 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000599
Uwe Hermann01ce6012010-03-05 10:03:50 +0000600 WARNING: This will produce a LOT of output and take a long time.
601
602 Note: This option will increase the size of the coreboot image.
603
604 If unsure, say N.
605
606config X86EMU_DEBUG_PNP
607 bool "Log Plug&Play accesses"
608 default n
609 depends on X86EMU_DEBUG
610 help
611 Print Plug And Play accesses made by option ROMs.
612
613 Note: This option will increase the size of the coreboot image.
614
615 If unsure, say N.
616
617config X86EMU_DEBUG_DISK
618 bool "Log Disk I/O"
619 default n
620 depends on X86EMU_DEBUG
621 help
622 Print Disk I/O related messages.
623
624 Note: This option will increase the size of the coreboot image.
625
626 If unsure, say N.
627
628config X86EMU_DEBUG_PMM
629 bool "Log PMM"
630 default n
631 depends on X86EMU_DEBUG
632 help
633 Print messages related to POST Memory Manager (PMM).
634
635 Note: This option will increase the size of the coreboot image.
636
637 If unsure, say N.
638
639
640config X86EMU_DEBUG_VBE
641 bool "Debug VESA BIOS Extensions"
642 default n
643 depends on X86EMU_DEBUG
644 help
645 Print messages related to VESA BIOS Extension (VBE) functions.
646
647 Note: This option will increase the size of the coreboot image.
648
649 If unsure, say N.
650
651config X86EMU_DEBUG_INT10
652 bool "Redirect INT10 output to console"
653 default n
654 depends on X86EMU_DEBUG
655 help
656 Let INT10 (i.e. character output) calls print messages to debug output.
657
658 Note: This option will increase the size of the coreboot image.
659
660 If unsure, say N.
661
662config X86EMU_DEBUG_INTERRUPTS
663 bool "Log intXX calls"
664 default n
665 depends on X86EMU_DEBUG
666 help
667 Print messages related to interrupt handling.
668
669 Note: This option will increase the size of the coreboot image.
670
671 If unsure, say N.
672
673config X86EMU_DEBUG_CHECK_VMEM_ACCESS
674 bool "Log special memory accesses"
675 default n
676 depends on X86EMU_DEBUG
677 help
678 Print messages related to accesses to certain areas of the virtual
679 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
680
681 Note: This option will increase the size of the coreboot image.
682
683 If unsure, say N.
684
685config X86EMU_DEBUG_MEM
686 bool "Log all memory accesses"
687 default n
688 depends on X86EMU_DEBUG
689 help
690 Print memory accesses made by option ROM.
691 Note: This also includes accesses to fetch instructions.
692
693 Note: This option will increase the size of the coreboot image.
694
695 If unsure, say N.
696
697config X86EMU_DEBUG_IO
698 bool "Log IO accesses"
699 default n
700 depends on X86EMU_DEBUG
701 help
702 Print I/O accesses made by option ROM.
703
704 Note: This option will increase the size of the coreboot image.
705
706 If unsure, say N.
707
Stefan Reinauer5c503922010-03-13 22:07:15 +0000708config LLSHELL
709 bool "Built-in low-level shell"
710 default n
711 help
712 If enabled, you will have a low level shell to examine your machine.
713 Put llshell() in your (romstage) code to start the shell.
714 See src/arch/i386/llshell/llshell.inc for details.
715
Uwe Hermann168b11b2009-10-07 16:15:40 +0000716endmenu
717
Myles Watson8f74c582009-10-20 16:10:04 +0000718config LIFT_BSP_APIC_ID
719 bool
720 default n
Myles Watsond73c1b52009-10-26 15:14:07 +0000721
722# These probably belong somewhere else, but they are needed somewhere.
723config AP_CODE_IN_CAR
724 bool
725 default n
726
Myles Watsond73c1b52009-10-26 15:14:07 +0000727config ENABLE_APIC_EXT_ID
728 bool
729 default n
Myles Watson2e672732009-11-12 16:38:03 +0000730
731config WARNINGS_ARE_ERRORS
732 bool
Stefan Reinauer6f57b512010-07-08 16:41:05 +0000733 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +0000734
735config ID_SECTION_OFFSET
736 hex
737 default 0x10
Patrick Georgicc669262010-03-14 21:31:05 +0000738
739source src/Kconfig.deprecated_options