Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 1 | config SOC_INTEL_JASPERLAKE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | bool |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | help |
| 4 | Intel Jasperlake support |
| 5 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 6 | if SOC_INTEL_JASPERLAKE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 11 | select ARCH_X86 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 13 | select CACHE_MRC_SETTINGS |
Sumeet R Pawnikar | e8d1bef | 2020-05-08 21:31:44 +0530 | [diff] [blame] | 14 | select CPU_INTEL_COMMON |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Aamir Bohra | 522ba1b | 2020-07-22 14:15:36 +0530 | [diff] [blame] | 17 | select COS_MAPPED_TO_MSB |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 18 | select DISPLAY_FSP_VERSION_INFO_2 |
Karthikeyan Ramasubramanian | 8021b47 | 2020-06-16 23:54:46 -0600 | [diff] [blame] | 19 | select FSP_COMPRESS_FSP_S_LZ4 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 20 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 21 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 22 | select GENERIC_GPIO_LIB |
| 23 | select HAVE_FSP_GOP |
| 24 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 25 | select HAVE_SMI_HANDLER |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 26 | select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 27 | select IDT_IN_EVERY_STAGE |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 28 | select INTEL_CAR_NEM_ENHANCED |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 29 | select INTEL_GMA_ACPI |
| 30 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 31 | select MP_SERVICES_PPI_V1 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 32 | select MRC_SETTINGS_PROTECT |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 33 | select PARALLEL_MP_AP_WORK |
Ronak Kanabar | 8c4ad35 | 2020-07-24 17:46:19 +0530 | [diff] [blame] | 34 | select PLATFORM_USES_FSP2_2 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 35 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 36 | select SOC_INTEL_COMMON |
| 37 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 38 | select SOC_INTEL_COMMON_BLOCK |
| 39 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Michael Niewöhner | 02275be | 2020-11-12 23:50:37 +0100 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Michael Niewöhner | 8a6c34e | 2021-01-01 21:26:42 +0100 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Tim Wawrzynczak | 77b36ab | 2021-07-01 08:44:14 -0600 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK_CAR |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 48 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| 51 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 52 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 53 | select SOC_INTEL_COMMON_BLOCK_SA |
Duncan Laurie | 1e06611 | 2020-04-08 11:35:52 -0700 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_SCS |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_SMM |
Sumeet R Pawnikar | e8d1bef | 2020-05-08 21:31:44 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Karthikeyan Ramasubramanian | af0d516 | 2020-11-04 17:05:35 -0700 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_FSP_RESET |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_PCH_BASE |
| 61 | select SOC_INTEL_COMMON_RESET |
Tim Wawrzynczak | 82eaa21 | 2021-06-17 12:44:36 -0600 | [diff] [blame] | 62 | select SOC_INTEL_CSE_SET_EOP |
Subrata Banik | af27ac2 | 2022-02-18 00:44:15 +0530 | [diff] [blame] | 63 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 64 | select SSE2 |
| 65 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 66 | select TSC_MONOTONIC_TIMER |
| 67 | select UDELAY_TSC |
Ronak Kanabar | a360aad | 2020-08-19 14:40:08 +0530 | [diff] [blame] | 68 | select UDK_202005_BINDING |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 69 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 70 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 71 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Sridhar Siricilla | afe5562 | 2022-03-16 23:36:30 +0530 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 73 | |
| 74 | config DCACHE_RAM_BASE |
| 75 | default 0xfef00000 |
| 76 | |
| 77 | config DCACHE_RAM_SIZE |
| 78 | default 0x80000 |
| 79 | help |
| 80 | The size of the cache-as-ram region required during bootblock |
| 81 | and/or romstage. |
| 82 | |
| 83 | config DCACHE_BSP_STACK_SIZE |
| 84 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 85 | default 0x30400 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 86 | help |
| 87 | The amount of anticipated stack usage in CAR by bootblock and |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 88 | other stages. In the case of FSP_USES_CB_STACK default value |
| 89 | will be sum of FSP-M stack requirement(192 KiB) and CB romstage |
| 90 | stack requirement(~1KiB). |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 91 | |
| 92 | config FSP_TEMP_RAM_SIZE |
| 93 | hex |
| 94 | default 0x20000 |
| 95 | help |
| 96 | The amount of anticipated heap usage in CAR by FSP. |
| 97 | Refer to Platform FSP integration guide document to know |
| 98 | the exact FSP requirement for Heap setup. |
| 99 | |
| 100 | config IFD_CHIPSET |
| 101 | string |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 102 | default "jsl" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 103 | |
| 104 | config IED_REGION_SIZE |
| 105 | hex |
| 106 | default 0x400000 |
| 107 | |
| 108 | config HEAP_SIZE |
| 109 | hex |
| 110 | default 0x8000 |
| 111 | |
| 112 | config MAX_ROOT_PORTS |
| 113 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 114 | default 8 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 115 | |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 116 | config MAX_PCIE_CLOCK_SRC |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 117 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 118 | default 6 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 119 | |
| 120 | config SMM_TSEG_SIZE |
| 121 | hex |
| 122 | default 0x800000 |
| 123 | |
| 124 | config SMM_RESERVED_SIZE |
| 125 | hex |
| 126 | default 0x200000 |
| 127 | |
| 128 | config PCR_BASE_ADDRESS |
| 129 | hex |
| 130 | default 0xfd000000 |
| 131 | help |
| 132 | This option allows you to select MMIO Base Address of sideband bus. |
| 133 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 134 | config ECAM_MMCONF_BASE_ADDRESS |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 135 | default 0xc0000000 |
| 136 | |
| 137 | config CPU_BCLK_MHZ |
| 138 | int |
| 139 | default 100 |
| 140 | |
| 141 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 142 | int |
| 143 | default 120 |
| 144 | |
| 145 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 146 | int |
| 147 | default 133 |
| 148 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 149 | config CPU_XTAL_HZ |
| 150 | default 38400000 |
| 151 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 152 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 153 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 154 | default 3 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 155 | |
| 156 | config SOC_INTEL_I2C_DEV_MAX |
| 157 | int |
| 158 | default 6 |
| 159 | |
| 160 | config SOC_INTEL_UART_DEV_MAX |
| 161 | int |
| 162 | default 3 |
| 163 | |
| 164 | config CONSOLE_UART_BASE_ADDRESS |
| 165 | hex |
| 166 | default 0xfe032000 |
| 167 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 168 | |
| 169 | # Clock divider parameters for 115200 baud rate |
| 170 | # Baudrate = (UART source clcok * M) /(N *16) |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 171 | # JSL UART source clock: 100MHz |
| 172 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 173 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 174 | default 0x30 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 175 | |
| 176 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 177 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 178 | default 0xc35 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 179 | |
Seunghwan Kim | 024b2bd | 2021-08-27 18:49:47 +0900 | [diff] [blame] | 180 | config VBT_DATA_SIZE_KB |
| 181 | int |
| 182 | default 9 |
| 183 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 184 | config VBOOT |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 185 | select VBOOT_MUST_REQUEST_DISPLAY |
| 186 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 187 | select VBOOT_VBNV_CMOS |
| 188 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 189 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 190 | config CBFS_SIZE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 191 | default 0x200000 |
| 192 | |
| 193 | config FSP_HEADER_PATH |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 194 | default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 195 | |
| 196 | config FSP_FD_PATH |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 197 | default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 198 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 199 | config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 200 | int "Debug Consent for JSL" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 201 | # USB DBC is more common for developers so make this default to 3 if |
| 202 | # SOC_INTEL_DEBUG_CONSENT=y |
| 203 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 204 | default 0 |
| 205 | help |
| 206 | This is to control debug interface on SOC. |
| 207 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 208 | PlatformDebugConsent in FspmUpd.h has the details. |
| 209 | |
| 210 | Desired platform debug type are |
| 211 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 212 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 213 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | ebf1daa | 2020-05-19 12:32:41 +0530 | [diff] [blame] | 214 | |
| 215 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 216 | hex |
Meera Ravindranath | 6aa6f1f | 2020-08-10 15:19:23 +0530 | [diff] [blame] | 217 | default 0x1400 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 218 | endif |