Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 1 | config SOC_INTEL_JASPERLAKE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | bool |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | help |
| 4 | Intel Jasperlake support |
| 5 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 6 | if SOC_INTEL_JASPERLAKE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 16 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 17 | select CACHE_MRC_SETTINGS |
| 18 | select COMMON_FADT |
| 19 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 20 | select FSP_M_XIP |
| 21 | select GENERIC_GPIO_LIB |
| 22 | select HAVE_FSP_GOP |
| 23 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 24 | select HAVE_SMI_HANDLER |
| 25 | select IDT_IN_EVERY_STAGE |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 26 | select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 27 | select INTEL_GMA_ACPI |
| 28 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 29 | select IOAPIC |
| 30 | select MRC_SETTINGS_PROTECT |
| 31 | select PARALLEL_MP |
| 32 | select PARALLEL_MP_AP_WORK |
| 33 | select MICROCODE_BLOB_UNDISCLOSED |
| 34 | select PLATFORM_USES_FSP2_1 |
| 35 | select REG_SCRIPT |
| 36 | select SMP |
| 37 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
| 38 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 39 | select CPU_INTEL_COMMON_SMM |
| 40 | select SOC_INTEL_COMMON |
| 41 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 42 | select SOC_INTEL_COMMON_BLOCK |
| 43 | select SOC_INTEL_COMMON_BLOCK_ACPI |
| 44 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| 45 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 46 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 47 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| 48 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 49 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 50 | select SOC_INTEL_COMMON_BLOCK_SA |
Duncan Laurie | 1e06611 | 2020-04-08 11:35:52 -0700 | [diff] [blame^] | 51 | select SOC_INTEL_COMMON_BLOCK_SCS |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 53 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
| 54 | select SOC_INTEL_COMMON_PCH_BASE |
| 55 | select SOC_INTEL_COMMON_RESET |
| 56 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 57 | select SSE2 |
| 58 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 59 | select TSC_MONOTONIC_TIMER |
| 60 | select UDELAY_TSC |
| 61 | select UDK_2017_BINDING |
| 62 | select DISPLAY_FSP_VERSION_INFO |
| 63 | select HECI_DISABLE_USING_SMM |
| 64 | |
| 65 | config DCACHE_RAM_BASE |
| 66 | default 0xfef00000 |
| 67 | |
| 68 | config DCACHE_RAM_SIZE |
| 69 | default 0x80000 |
| 70 | help |
| 71 | The size of the cache-as-ram region required during bootblock |
| 72 | and/or romstage. |
| 73 | |
| 74 | config DCACHE_BSP_STACK_SIZE |
| 75 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 76 | default 0x30400 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 77 | help |
| 78 | The amount of anticipated stack usage in CAR by bootblock and |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 79 | other stages. In the case of FSP_USES_CB_STACK default value |
| 80 | will be sum of FSP-M stack requirement(192 KiB) and CB romstage |
| 81 | stack requirement(~1KiB). |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 82 | |
| 83 | config FSP_TEMP_RAM_SIZE |
| 84 | hex |
| 85 | default 0x20000 |
| 86 | help |
| 87 | The amount of anticipated heap usage in CAR by FSP. |
| 88 | Refer to Platform FSP integration guide document to know |
| 89 | the exact FSP requirement for Heap setup. |
| 90 | |
| 91 | config IFD_CHIPSET |
| 92 | string |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 93 | default "jsl" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 94 | |
| 95 | config IED_REGION_SIZE |
| 96 | hex |
| 97 | default 0x400000 |
| 98 | |
| 99 | config HEAP_SIZE |
| 100 | hex |
| 101 | default 0x8000 |
| 102 | |
| 103 | config MAX_ROOT_PORTS |
| 104 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 105 | default 8 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 106 | |
| 107 | config MAX_PCIE_CLOCKS |
| 108 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 109 | default 6 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 110 | |
| 111 | config SMM_TSEG_SIZE |
| 112 | hex |
| 113 | default 0x800000 |
| 114 | |
| 115 | config SMM_RESERVED_SIZE |
| 116 | hex |
| 117 | default 0x200000 |
| 118 | |
| 119 | config PCR_BASE_ADDRESS |
| 120 | hex |
| 121 | default 0xfd000000 |
| 122 | help |
| 123 | This option allows you to select MMIO Base Address of sideband bus. |
| 124 | |
| 125 | config MMCONF_BASE_ADDRESS |
| 126 | hex |
| 127 | default 0xc0000000 |
| 128 | |
| 129 | config CPU_BCLK_MHZ |
| 130 | int |
| 131 | default 100 |
| 132 | |
| 133 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 134 | int |
| 135 | default 120 |
| 136 | |
| 137 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 138 | int |
| 139 | default 133 |
| 140 | |
| 141 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 142 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 143 | default 3 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 144 | |
| 145 | config SOC_INTEL_I2C_DEV_MAX |
| 146 | int |
| 147 | default 6 |
| 148 | |
| 149 | config SOC_INTEL_UART_DEV_MAX |
| 150 | int |
| 151 | default 3 |
| 152 | |
| 153 | config CONSOLE_UART_BASE_ADDRESS |
| 154 | hex |
| 155 | default 0xfe032000 |
| 156 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 157 | |
| 158 | # Clock divider parameters for 115200 baud rate |
| 159 | # Baudrate = (UART source clcok * M) /(N *16) |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 160 | # JSL UART source clock: 100MHz |
| 161 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 162 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 163 | default 0x30 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 164 | |
| 165 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 166 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 167 | default 0xc35 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 168 | |
| 169 | config CHROMEOS |
| 170 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 171 | |
| 172 | config VBOOT |
| 173 | select VBOOT_SEPARATE_VERSTAGE |
| 174 | select VBOOT_MUST_REQUEST_DISPLAY |
| 175 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 176 | select VBOOT_VBNV_CMOS |
| 177 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 178 | |
| 179 | config C_ENV_BOOTBLOCK_SIZE |
| 180 | hex |
| 181 | default 0xC000 |
| 182 | |
| 183 | config CBFS_SIZE |
| 184 | hex |
| 185 | default 0x200000 |
| 186 | |
| 187 | config FSP_HEADER_PATH |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 188 | default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 189 | |
| 190 | config FSP_FD_PATH |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 191 | default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 192 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 193 | config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 194 | int "Debug Consent for JSL" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 195 | # USB DBC is more common for developers so make this default to 3 if |
| 196 | # SOC_INTEL_DEBUG_CONSENT=y |
| 197 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 198 | default 0 |
| 199 | help |
| 200 | This is to control debug interface on SOC. |
| 201 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 202 | PlatformDebugConsent in FspmUpd.h has the details. |
| 203 | |
| 204 | Desired platform debug type are |
| 205 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 206 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 207 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 208 | endif |