Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 3 | #include <arch/io.h> |
| 4 | #include <cbmem.h> |
Elyes HAOUAS | 5db9871 | 2019-04-21 18:50:34 +0200 | [diff] [blame] | 5 | #include <cf9_reset.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 6 | #include <console/console.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 7 | #include <device/pci_def.h> |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
| 9 | #include <device/pci.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 10 | #include <option.h> |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 11 | #include <romstage_handoff.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 12 | #include <types.h> |
| 13 | |
| 14 | #include "i945.h" |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 15 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 16 | int i945_silicon_revision(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 17 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 18 | return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 19 | } |
| 20 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 21 | static void i945m_detect_chipset(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 22 | { |
| 23 | u8 reg8; |
| 24 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 25 | printk(BIOS_INFO, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 26 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
| 27 | switch (reg8) { |
| 28 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 29 | printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 30 | break; |
| 31 | case 2: |
Stefan Reinauer | 7981b94 | 2011-04-01 22:33:25 +0200 | [diff] [blame] | 32 | printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 33 | break; |
| 34 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 35 | printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 36 | break; |
| 37 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 38 | printk(BIOS_INFO, "Intel(R) 82945GT Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 39 | break; |
| 40 | case 6: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 41 | printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 42 | break; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 43 | default: /* Others reserved. */ |
| 44 | printk(BIOS_INFO, "Unknown (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 45 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 46 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 47 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 48 | printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 49 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; |
| 50 | switch (reg8) { |
| 51 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 52 | printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 53 | break; |
| 54 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 55 | printk(BIOS_DEBUG, "667 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 56 | break; |
| 57 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 58 | printk(BIOS_DEBUG, "533 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 59 | break; |
| 60 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 61 | printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 62 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 63 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 64 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 66 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 67 | switch (reg8) { |
| 68 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 69 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 70 | break; |
| 71 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 72 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 73 | break; |
| 74 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 75 | printk(BIOS_DEBUG, "DDR2-400"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 76 | break; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 77 | default: /* Others reserved. */ |
| 78 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 79 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 80 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 81 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 82 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 83 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 84 | } |
| 85 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 86 | static void i945_detect_chipset(void) |
| 87 | { |
| 88 | u8 reg8; |
| 89 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 90 | printk(BIOS_INFO, "\nIntel(R) "); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 91 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 92 | reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) |
| 93 | | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 94 | switch (reg8) { |
| 95 | case 0: |
| 96 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 97 | printk(BIOS_INFO, "82945G"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 98 | break; |
| 99 | case 2: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 100 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 101 | printk(BIOS_INFO, "82945P"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 102 | break; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 103 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 104 | printk(BIOS_INFO, "82945GC"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 105 | break; |
| 106 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 107 | printk(BIOS_INFO, "82945GZ"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 108 | break; |
| 109 | case 6: |
| 110 | case 7: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 111 | printk(BIOS_INFO, "82945PL"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 112 | break; |
| 113 | default: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 114 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 115 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 116 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 117 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 118 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 119 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 120 | switch (reg8) { |
| 121 | case 0: |
Elyes HAOUAS | 5db9450 | 2016-10-30 18:30:21 +0100 | [diff] [blame] | 122 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 123 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 124 | break; |
| 125 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 126 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 127 | break; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 128 | default: /* Others reserved. */ |
| 129 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 130 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 131 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 132 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 133 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 134 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 135 | } |
| 136 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 137 | static void i945_setup_bars(void) |
| 138 | { |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 139 | u8 reg8, gfxsize; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 140 | |
| 141 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 142 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 143 | printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 144 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 145 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 146 | /* Set up all hardcoded northbridge BARs */ |
| 147 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 148 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 149 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 150 | pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |
| 151 | |
Elyes HAOUAS | 2119d0b | 2020-02-16 10:01:33 +0100 | [diff] [blame] | 152 | /* vram size from CMOS option */ |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 153 | if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) |
| 154 | gfxsize = 2; /* 2 for 8MB */ |
| 155 | /* make sure no invalid setting is used */ |
| 156 | if (gfxsize > 6) |
| 157 | gfxsize = 2; |
| 158 | pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 159 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 160 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 161 | pci_update_config8(PCI_DEV(0, 0, 0), ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); |
Arthur Heymans | e07df9d | 2018-04-09 22:03:21 +0200 | [diff] [blame] | 162 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 163 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 164 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 165 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 166 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 167 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 168 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 169 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 170 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 171 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 172 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 173 | |
| 174 | /* Wait for MCH BAR to come up */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 175 | printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); |
Elyes HAOUAS | a3ea1e4 | 2014-11-27 13:23:32 +0100 | [diff] [blame] | 176 | if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 177 | do { |
| 178 | reg8 = *(volatile u8 *)0xfed40000; |
| 179 | } while (!(reg8 & 0x80)); |
| 180 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 181 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | static void i945_setup_egress_port(void) |
| 185 | { |
| 186 | u32 reg32; |
| 187 | u32 timeout; |
| 188 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 189 | printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 190 | |
| 191 | /* Egress Port Virtual Channel 0 Configuration */ |
| 192 | |
| 193 | /* map only TC0 to VC0 */ |
| 194 | reg32 = EPBAR32(EPVC0RCTL); |
| 195 | reg32 &= 0xffffff01; |
| 196 | EPBAR32(EPVC0RCTL) = reg32; |
| 197 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 198 | reg32 = EPBAR32(EPPVCCAP1); |
| 199 | reg32 &= ~(7 << 0); |
| 200 | reg32 |= 1; |
| 201 | EPBAR32(EPPVCCAP1) = reg32; |
| 202 | |
| 203 | /* Egress Port Virtual Channel 1 Configuration */ |
| 204 | reg32 = EPBAR32(0x2c); |
| 205 | reg32 &= 0xffffff00; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 206 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 207 | if ((MCHBAR32(CLKCFG) & 7) == 0) |
| 208 | reg32 |= 0x1a; /* 1067MHz */ |
| 209 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 210 | if ((MCHBAR32(CLKCFG) & 7) == 1) |
| 211 | reg32 |= 0x0d; /* 533MHz */ |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 212 | if ((MCHBAR32(CLKCFG) & 7) == 2) |
| 213 | reg32 |= 0x14; /* 800MHz */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 214 | if ((MCHBAR32(CLKCFG) & 7) == 3) |
| 215 | reg32 |= 0x10; /* 667MHz */ |
| 216 | EPBAR32(0x2c) = reg32; |
| 217 | |
| 218 | EPBAR32(EPVC1MTS) = 0x0a0a0a0a; |
| 219 | |
| 220 | reg32 = EPBAR32(EPVC1RCAP); |
| 221 | reg32 &= ~(0x7f << 16); |
| 222 | reg32 |= (0x0a << 16); |
| 223 | EPBAR32(EPVC1RCAP) = reg32; |
| 224 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 225 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 226 | if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */ |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 227 | EPBAR32(EPVC1IST + 0) = 0x01380138; |
| 228 | EPBAR32(EPVC1IST + 4) = 0x01380138; |
| 229 | } |
| 230 | } |
| 231 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 232 | if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 233 | EPBAR32(EPVC1IST + 0) = 0x009c009c; |
| 234 | EPBAR32(EPVC1IST + 4) = 0x009c009c; |
| 235 | } |
| 236 | |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 237 | if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ |
| 238 | EPBAR32(EPVC1IST + 0) = 0x00f000f0; |
| 239 | EPBAR32(EPVC1IST + 4) = 0x00f000f0; |
| 240 | } |
| 241 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 242 | if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 243 | EPBAR32(EPVC1IST + 0) = 0x00c000c0; |
| 244 | EPBAR32(EPVC1IST + 4) = 0x00c000c0; |
| 245 | } |
| 246 | |
| 247 | /* Is internal graphics enabled? */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 248 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 249 | MCHBAR32(MMARB1) |= (1 << 17); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 250 | |
| 251 | /* Assign Virtual Channel ID 1 to VC1 */ |
| 252 | reg32 = EPBAR32(EPVC1RCTL); |
| 253 | reg32 &= ~(7 << 24); |
| 254 | reg32 |= (1 << 24); |
| 255 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 256 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 257 | reg32 = EPBAR32(EPVC1RCTL); |
| 258 | reg32 &= 0xffffff01; |
| 259 | reg32 |= (1 << 7); |
| 260 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 261 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 262 | EPBAR32(PORTARB + 0x00) = 0x01000001; |
| 263 | EPBAR32(PORTARB + 0x04) = 0x00040000; |
| 264 | EPBAR32(PORTARB + 0x08) = 0x00001000; |
| 265 | EPBAR32(PORTARB + 0x0c) = 0x00000040; |
| 266 | EPBAR32(PORTARB + 0x10) = 0x01000001; |
| 267 | EPBAR32(PORTARB + 0x14) = 0x00040000; |
| 268 | EPBAR32(PORTARB + 0x18) = 0x00001000; |
| 269 | EPBAR32(PORTARB + 0x1c) = 0x00000040; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 270 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 271 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 272 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 273 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 274 | printk(BIOS_DEBUG, "Loading port arbitration table ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 275 | /* Loop until bit 0 becomes 0 */ |
| 276 | timeout = 0x7fffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 277 | while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) |
| 278 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 279 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 280 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 281 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 282 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 283 | |
| 284 | /* Now enable VC1 */ |
| 285 | EPBAR32(EPVC1RCTL) |= (1 << 31); |
| 286 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 287 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 288 | /* Wait for VC1 negotiation pending */ |
| 289 | timeout = 0x7fff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 290 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) |
| 291 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 292 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 293 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 294 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 295 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 296 | |
| 297 | } |
| 298 | |
| 299 | static void ich7_setup_dmi_rcrb(void) |
| 300 | { |
| 301 | u16 reg16; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 302 | u32 reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 303 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 304 | reg16 = RCBA16(LCTL); |
| 305 | reg16 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 306 | reg16 |= 3; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 307 | RCBA16(LCTL) = reg16; |
| 308 | |
| 309 | RCBA32(V0CTL) = 0x80000001; |
| 310 | RCBA32(V1CAP) = 0x03128010; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 311 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 312 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 313 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 314 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 315 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 316 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 317 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 318 | |
| 319 | reg32 = RCBA32(V1CTL); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 320 | reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 321 | reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); |
| 322 | RCBA32(V1CTL) = reg32; |
| 323 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 324 | RCBA32(LCAP) |= (3 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | static void i945_setup_dmi_rcrb(void) |
| 328 | { |
| 329 | u32 reg32; |
| 330 | u32 timeout; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 331 | int activate_aspm = 1; /* hardcode ASPM for now */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 332 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 333 | printk(BIOS_DEBUG, "Setting up DMI RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 334 | |
| 335 | /* Virtual Channel 0 Configuration */ |
| 336 | reg32 = DMIBAR32(DMIVC0RCTL0); |
| 337 | reg32 &= 0xffffff01; |
| 338 | DMIBAR32(DMIVC0RCTL0) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 339 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 340 | reg32 = DMIBAR32(DMIPVCCAP1); |
| 341 | reg32 &= ~(7 << 0); |
| 342 | reg32 |= 1; |
| 343 | DMIBAR32(DMIPVCCAP1) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 344 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 345 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 346 | reg32 &= ~(7 << 24); |
| 347 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
| 348 | DMIBAR32(DMIVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 349 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 350 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 351 | reg32 &= 0xffffff01; |
| 352 | reg32 |= (1 << 7); |
| 353 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 354 | |
| 355 | /* Now enable VC1 */ |
| 356 | DMIBAR32(DMIVC1RCTL) |= (1 << 31); |
| 357 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 358 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 359 | /* Wait for VC1 negotiation pending */ |
| 360 | timeout = 0x7ffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 361 | while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) |
| 362 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 363 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 364 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 365 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 366 | printk(BIOS_DEBUG, "done..\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 367 | #if 1 |
| 368 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 369 | |
| 370 | reg32 = DMIBAR32(DMILCAP); |
| 371 | reg32 &= ~(7 << 12); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 372 | reg32 |= (2 << 12); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 373 | |
| 374 | reg32 &= ~(7 << 15); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 375 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 376 | reg32 |= (2 << 15); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 377 | DMIBAR32(DMILCAP) = reg32; |
| 378 | |
| 379 | reg32 = DMIBAR32(DMICC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 380 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 381 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 382 | reg32 |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 383 | reg32 &= ~(3 << 20); |
| 384 | reg32 |= (1 << 20); |
| 385 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 386 | DMIBAR32(DMICC) = reg32; |
| 387 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 388 | if (activate_aspm) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 389 | DMIBAR32(DMILCTL) |= (3 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 390 | #endif |
| 391 | |
| 392 | /* Last but not least, some additional steps */ |
| 393 | reg32 = MCHBAR32(FSBSNPCTL); |
| 394 | reg32 &= ~(0xff << 2); |
| 395 | reg32 |= (0xaa << 2); |
| 396 | MCHBAR32(FSBSNPCTL) = reg32; |
| 397 | |
| 398 | DMIBAR32(0x2c) = 0x86000040; |
| 399 | |
| 400 | reg32 = DMIBAR32(0x204); |
| 401 | reg32 &= ~0x3ff; |
| 402 | #if 1 |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 403 | reg32 |= 0x13f; /* for x4 DMI only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 404 | #else |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 405 | reg32 |= 0x1e4; /* for x2 DMI only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 406 | #endif |
| 407 | DMIBAR32(0x204) = reg32; |
| 408 | |
Kyösti Mälkki | 3c3e34d | 2014-05-31 11:32:54 +0300 | [diff] [blame] | 409 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 410 | printk(BIOS_DEBUG, "Internal graphics: enabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 411 | DMIBAR32(0x200) |= (1 << 21); |
| 412 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 413 | printk(BIOS_DEBUG, "Internal graphics: disabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 414 | DMIBAR32(0x200) &= ~(1 << 21); |
| 415 | } |
| 416 | |
| 417 | reg32 = DMIBAR32(0x204); |
| 418 | reg32 &= ~((1 << 11) | (1 << 10)); |
| 419 | DMIBAR32(0x204) = reg32; |
| 420 | |
| 421 | reg32 = DMIBAR32(0x204); |
| 422 | reg32 &= ~(0xff << 12); |
| 423 | reg32 |= (0x0d << 12); |
| 424 | DMIBAR32(0x204) = reg32; |
| 425 | |
| 426 | DMIBAR32(DMICTL1) |= (3 << 24); |
| 427 | |
| 428 | reg32 = DMIBAR32(0x200); |
| 429 | reg32 &= ~(0x3 << 26); |
| 430 | reg32 |= (0x02 << 26); |
| 431 | DMIBAR32(0x200) = reg32; |
| 432 | |
| 433 | DMIBAR32(DMIDRCCFG) &= ~(1 << 31); |
| 434 | DMIBAR32(DMICTL2) |= (1 << 31); |
| 435 | |
| 436 | if (i945_silicon_revision() >= 3) { |
| 437 | reg32 = DMIBAR32(0xec0); |
| 438 | reg32 &= 0x0fffffff; |
| 439 | reg32 |= (2 << 28); |
| 440 | DMIBAR32(0xec0) = reg32; |
| 441 | |
| 442 | reg32 = DMIBAR32(0xed4); |
| 443 | reg32 &= 0x0fffffff; |
| 444 | reg32 |= (2 << 28); |
| 445 | DMIBAR32(0xed4) = reg32; |
| 446 | |
| 447 | reg32 = DMIBAR32(0xee8); |
| 448 | reg32 &= 0x0fffffff; |
| 449 | reg32 |= (2 << 28); |
| 450 | DMIBAR32(0xee8) = reg32; |
| 451 | |
| 452 | reg32 = DMIBAR32(0xefc); |
| 453 | reg32 &= 0x0fffffff; |
| 454 | reg32 |= (2 << 28); |
| 455 | DMIBAR32(0xefc) = reg32; |
| 456 | } |
| 457 | |
| 458 | /* wait for bit toggle to 0 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 459 | printk(BIOS_DEBUG, "Waiting for DMI hardware..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 460 | timeout = 0x7fffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 461 | while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) |
| 462 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 463 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 464 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 465 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 466 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 467 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 468 | /* Clear Error Status Bits! */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 469 | DMIBAR32(0x1c4) = 0xffffffff; |
| 470 | DMIBAR32(0x1d0) = 0xffffffff; |
| 471 | DMIBAR32(0x228) = 0xffffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 472 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 473 | /* Program Read-Only Write-Once Registers */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 474 | DMIBAR32(0x308) = DMIBAR32(0x308); |
| 475 | DMIBAR32(0x314) = DMIBAR32(0x314); |
| 476 | DMIBAR32(0x324) = DMIBAR32(0x324); |
| 477 | DMIBAR32(0x328) = DMIBAR32(0x328); |
Elyes HAOUAS | d3fa7fa5 | 2019-01-24 11:47:27 +0100 | [diff] [blame] | 478 | DMIBAR32(0x334) = DMIBAR32(0x334); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 479 | DMIBAR32(0x338) = DMIBAR32(0x338); |
| 480 | |
Patrick Georgi | a341a77 | 2014-09-29 19:51:21 +0200 | [diff] [blame] | 481 | if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & (1 << 5))) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 482 | if ((MCHBAR32(0x214) & 0xf) != 0x3) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 483 | printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 484 | reg32 = DMIBAR32(0x224); |
| 485 | reg32 &= ~(7 << 0); |
| 486 | reg32 |= (3 << 0); |
| 487 | DMIBAR32(0x224) = reg32; |
Elyes HAOUAS | 5db9871 | 2019-04-21 18:50:34 +0200 | [diff] [blame] | 488 | system_reset(); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 489 | } |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | static void i945_setup_pci_express_x16(void) |
| 494 | { |
| 495 | u32 timeout; |
| 496 | u32 reg32; |
| 497 | u16 reg16; |
Elyes HAOUAS | 961658f | 2020-04-06 09:42:21 +0200 | [diff] [blame] | 498 | const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 499 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 500 | u8 tmp_secondary = 0x0a; |
Elyes HAOUAS | 961658f | 2020-04-06 09:42:21 +0200 | [diff] [blame] | 501 | const pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 502 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 503 | printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 504 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 505 | pci_or_config16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 506 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 507 | pci_and_config32(p2peg, PEGCC, ~(1 << 8)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 508 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 509 | /* We have no success with querying the usual PCIe registers |
| 510 | * for link setup success on the i945. Hence we assign a temporary |
| 511 | * PCI bus 0x0a and check whether we find a device on 0:a.0 |
| 512 | */ |
| 513 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 514 | /* Force PCIRST# */ |
| 515 | pci_s_assert_secondary_reset(p2peg); |
| 516 | pci_s_deassert_secondary_reset(p2peg); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 517 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 518 | reg16 = pci_read_config16(p2peg, SLOTSTS); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 519 | printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 520 | if (!(reg16 & 0x48)) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 521 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 522 | reg16 |= (1 << 4) | (1 << 0); |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 523 | pci_write_config16(p2peg, SLOTSTS, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 524 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 525 | pci_s_bridge_set_secondary(p2peg, tmp_secondary); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 526 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 527 | pci_and_config32(p2peg, 0x224, ~(1 << 8)); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 528 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 529 | MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 530 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 531 | /* Initialize PEG_CAP */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 532 | pci_or_config16(p2peg, PEG_CAP, 1 << 8); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 533 | |
| 534 | /* Setup SLOTCAP */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 535 | /* TODO: These values are mainboard dependent and should be set from devicetree.cb. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 536 | */ |
| 537 | /* NOTE: SLOTCAP becomes RO after the first write! */ |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 538 | reg32 = pci_read_config32(p2peg, SLOTCAP); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 539 | reg32 &= 0x0007ffff; |
| 540 | |
| 541 | reg32 &= 0xfffe007f; |
| 542 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 543 | pci_write_config32(p2peg, SLOTCAP, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 544 | |
| 545 | /* Wait for training to succeed */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 546 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 547 | timeout = 0x7ffff; |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 548 | while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 549 | ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 550 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 551 | reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 552 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 553 | printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 554 | reg32 & 0xffff, reg32 >> 16); |
| 555 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 556 | printk(BIOS_DEBUG, " timeout!\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 557 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 558 | printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 559 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 560 | pci_update_config32(p2peg, PEGSTS, ~(0xf << 1), 1); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 561 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 562 | /* Force PCIRST# */ |
| 563 | pci_s_assert_secondary_reset(p2peg); |
| 564 | pci_s_deassert_secondary_reset(p2peg); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 565 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 566 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 567 | timeout = 0x7ffff; |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 568 | while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 569 | ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 570 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 571 | reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 572 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 573 | printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 574 | reg32 & 0xffff, reg32 >> 16); |
| 575 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 576 | printk(BIOS_DEBUG, " timeout!\n"); |
| 577 | printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 578 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 579 | } |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 580 | } |
| 581 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 582 | reg16 = pci_read_config16(p2peg, 0xb2); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 583 | reg16 >>= 4; |
| 584 | reg16 &= 0x3f; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 585 | /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 586 | printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 587 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 588 | reg32 = pci_read_config32(p2peg, PEGTC); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 589 | reg32 &= 0xfffffc00; /* clear [9:0] */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 590 | if (reg16 == 1) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 591 | reg32 |= 0x32b; |
| 592 | // TODO |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 593 | /* pci_write_config32(p2peg, PEGTC, reg32); */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 594 | else if (reg16 == 16) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 595 | reg32 |= 0x0f4; |
| 596 | // TODO |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 597 | /* pci_write_config32(p2peg, PEGTC, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 598 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 599 | reg32 = (pci_read_config32(peg_plugin, 0x8) >> 8); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 600 | printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 601 | if (reg32 == 0x030000) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 602 | printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 603 | reg16 = (1 << 1); |
Elyes HAOUAS | ef20ecc | 2018-10-04 13:50:14 +0200 | [diff] [blame] | 604 | pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 605 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 606 | pci_and_config32(PCI_DEV(0, 0x0, 0), DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 607 | } |
| 608 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 609 | /* Enable GPEs: PMEGPE, HPGPE, GENGPE */ |
| 610 | pci_or_config32(p2peg, PEG_LC, (1 << 2) | (1 << 1) | (1 << 0)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 611 | |
| 612 | /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 613 | pci_and_config32(p2peg, VC0RCTL, ~0x000000fe); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 614 | |
| 615 | /* Extended VC count */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 616 | pci_and_config32(p2peg, PVCCAP1, ~(7 << 0)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 617 | |
| 618 | /* Active State Power Management ASPM */ |
| 619 | |
| 620 | /* TODO */ |
| 621 | |
| 622 | /* Clear error bits */ |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 623 | pci_write_config16(p2peg, PCISTS1, 0xffff); |
| 624 | pci_write_config16(p2peg, SSTS1, 0xffff); |
| 625 | pci_write_config16(p2peg, DSTS, 0xffff); |
| 626 | pci_write_config32(p2peg, UESTS, 0xffffffff); |
| 627 | pci_write_config32(p2peg, CESTS, 0xffffffff); |
| 628 | pci_write_config32(p2peg, 0x1f0, 0xffffffff); |
| 629 | pci_write_config32(p2peg, 0x228, 0xffffffff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 630 | |
| 631 | /* Program R/WO registers */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 632 | pci_update_config32(p2peg, 0x308, ~0, 0); |
| 633 | pci_update_config32(p2peg, 0x314, ~0, 0); |
| 634 | pci_update_config32(p2peg, 0x324, ~0, 0); |
| 635 | pci_update_config32(p2peg, 0x328, ~0, 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 636 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 637 | /* Additional PCIe graphics setup */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 638 | pci_or_config32(p2peg, 0xf0, 3 << 26); |
| 639 | pci_or_config32(p2peg, 0xf0, 3 << 24); |
| 640 | pci_or_config32(p2peg, 0xf0, 1 << 5); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 641 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 642 | pci_update_config32(p2peg, 0x200, ~(3 << 26), 2 << 26); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 643 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 644 | reg32 = pci_read_config32(p2peg, 0xe80); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 645 | if (i945_silicon_revision() >= 2) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 646 | reg32 |= (1 << 12); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 647 | else |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 648 | reg32 &= ~(1 << 12); |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 649 | pci_write_config32(p2peg, 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 650 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 651 | pci_and_config32(p2peg, 0xeb4, ~(1 << 31)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 652 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 653 | pci_or_config32(p2peg, 0xfc, 1 << 31); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 654 | |
| 655 | if (i945_silicon_revision() >= 3) { |
| 656 | static const u32 reglist[] = { |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 657 | 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, 0xf38, 0xf4c, |
| 658 | 0xf60, 0xf74, 0xf88, 0xf9c, 0xfb0, 0xfc4, 0xfd8, 0xfec |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 659 | }; |
| 660 | |
| 661 | int i; |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 662 | for (i = 0; i < ARRAY_SIZE(reglist); i++) |
| 663 | pci_update_config32(p2peg, reglist[i], ~(0xf << 28), 2 << 28); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 664 | } |
| 665 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 666 | if (i945_silicon_revision() <= 2) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 667 | /* Set voltage specific parameters */ |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 668 | reg32 = pci_read_config32(p2peg, 0xe80); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 669 | reg32 &= (0xf << 4); /* Default case 1.05V */ |
Patrick Georgi | 3cb86de | 2014-09-29 20:42:33 +0200 | [diff] [blame] | 670 | if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 671 | reg32 |= (7 << 4); |
| 672 | } |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 673 | pci_write_config32(p2peg, 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 674 | } |
| 675 | |
| 676 | return; |
| 677 | |
| 678 | disable_pciexpress_x16_link: |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 679 | /* For now we just disable the x16 link */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 680 | printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 681 | |
| 682 | MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); |
| 683 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 684 | /* Toggle PCIRST# */ |
| 685 | pci_s_assert_secondary_reset(p2peg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 686 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 687 | pci_or_config32(p2peg, 0x224, 1 << 8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 688 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 689 | pci_s_deassert_secondary_reset(p2peg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 690 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 691 | printk(BIOS_DEBUG, "Wait for link to enter detect state... "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 692 | timeout = 0x7fffff; |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 693 | for (reg32 = pci_read_config32(p2peg, PEGSTS); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 694 | (reg32 & 0x000f0000) && --timeout;) |
| 695 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 696 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 697 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 698 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 699 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 700 | |
| 701 | /* Finally: Disable the PCI config header */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 702 | pci_and_config16(PCI_DEV(0, 0x00, 0), DEVEN, ~DEVEN_D1F0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 703 | } |
| 704 | |
| 705 | static void i945_setup_root_complex_topology(void) |
| 706 | { |
| 707 | u32 reg32; |
Elyes HAOUAS | 961658f | 2020-04-06 09:42:21 +0200 | [diff] [blame] | 708 | const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 709 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 710 | printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 711 | /* Egress Port Root Topology */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 712 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 713 | reg32 = EPBAR32(EPESD); |
| 714 | reg32 &= 0xff00ffff; |
| 715 | reg32 |= (1 << 16); |
| 716 | EPBAR32(EPESD) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 717 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 718 | EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 719 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 720 | EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 721 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 722 | EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 723 | |
| 724 | /* DMI Port Root Topology */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 725 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 726 | reg32 = DMIBAR32(DMILE1D); |
| 727 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 728 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 729 | reg32 &= 0xff00ffff; |
| 730 | reg32 |= (2 << 16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 731 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 732 | reg32 |= (1 << 0); |
| 733 | DMIBAR32(DMILE1D) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 734 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 735 | DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 736 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 737 | DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 738 | |
| 739 | DMIBAR32(DMILE2A) = DEFAULT_EPBAR; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 740 | |
| 741 | /* PCI Express x16 Port Root Topology */ |
| 742 | if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 743 | pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 744 | pci_or_config32(p2peg, LE1D, 1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 745 | } |
| 746 | } |
| 747 | |
| 748 | static void ich7_setup_root_complex_topology(void) |
| 749 | { |
Elyes HAOUAS | b217baa | 2019-01-18 15:32:39 +0100 | [diff] [blame] | 750 | /* Write the R/WO registers */ |
| 751 | |
| 752 | RCBA32(ESD) |= (2 << 16); |
| 753 | |
| 754 | RCBA32(ULD) |= (1 << 24) | (1 << 16); |
| 755 | |
| 756 | RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; |
| 757 | /* Write ESD.CID to TCID */ |
| 758 | RCBA32(RP1D) |= (2 << 16); |
| 759 | RCBA32(RP2D) |= (2 << 16); |
| 760 | RCBA32(RP3D) |= (2 << 16); |
| 761 | RCBA32(RP4D) |= (2 << 16); |
| 762 | RCBA32(HDD) |= (2 << 16); |
| 763 | RCBA32(RP5D) |= (2 << 16); |
| 764 | RCBA32(RP6D) |= (2 << 16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 765 | } |
| 766 | |
| 767 | static void ich7_setup_pci_express(void) |
| 768 | { |
Elyes HAOUAS | 1374607 | 2019-12-08 11:34:24 +0100 | [diff] [blame] | 769 | /* Enable PCIe Root Port Clock Gate */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 770 | RCBA32(CG) |= (1 << 0); |
| 771 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 772 | /* Initialize slot power limit for root ports */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 773 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 774 | #if 0 |
| 775 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 776 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 777 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 778 | |
| 779 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 780 | } |
| 781 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 782 | void i945_early_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 783 | { |
| 784 | /* Print some chipset specific information */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 785 | switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 786 | case 0x27708086: /* 82945G/GZ/GC/P/PL */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 787 | i945_detect_chipset(); |
| 788 | break; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 789 | case 0x27a08086: /* 945GME/GSE */ |
| 790 | case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 791 | i945m_detect_chipset(); |
| 792 | break; |
| 793 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 794 | |
| 795 | /* Setup all BARs required for early PCIe and raminit */ |
| 796 | i945_setup_bars(); |
| 797 | |
| 798 | /* Change port80 to LPC */ |
| 799 | RCBA32(GCS) &= (~0x04); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 800 | |
| 801 | /* Just do it that way */ |
| 802 | RCBA32(0x2010) |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 803 | } |
| 804 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 805 | static void i945_prepare_resume(int s3resume) |
| 806 | { |
| 807 | int cbmem_was_initted; |
| 808 | |
| 809 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 810 | |
Kyösti Mälkki | 8183025 | 2016-06-25 11:40:00 +0300 | [diff] [blame] | 811 | romstage_handoff_init(cbmem_was_initted && s3resume); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 812 | } |
| 813 | |
| 814 | void i945_late_initialization(int s3resume) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 815 | { |
| 816 | i945_setup_egress_port(); |
| 817 | |
| 818 | ich7_setup_root_complex_topology(); |
| 819 | |
| 820 | ich7_setup_pci_express(); |
| 821 | |
| 822 | ich7_setup_dmi_rcrb(); |
| 823 | |
| 824 | i945_setup_dmi_rcrb(); |
| 825 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 826 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 827 | i945_setup_pci_express_x16(); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 828 | |
| 829 | i945_setup_root_complex_topology(); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 830 | |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 831 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 832 | sdram_dump_mchbar_registers(); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 833 | |
| 834 | MCHBAR16(SSKPD) = 0xCAFE; |
| 835 | |
| 836 | i945_prepare_resume(s3resume); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 837 | } |