Gitiles
Code Review Sign In
review.coreboot.org / coreboot / eef4343a9f0e94a5a2137793d15c582278715d28 / . / src / southbridge / intel / common / Kconfig
blob: a14513deadd39038192927b40a13817088b5856f [file] [log] [blame]
Patrick Rudolph45022ae2018-10-01 19:17:11 +0200[diff] [blame]1config SOUTHBRIDGE_INTEL_COMMON_RESET
Arthur Heymans23a6c792019-10-13 22:36:04 +0200[diff] [blame]2 def_bool n
Patrick Rudolph45022ae2018-10-01 19:17:11 +0200[diff] [blame]3 select HAVE_CF9_RESET
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]4
Arthur Heymans074730c2019-06-04 14:05:53 +0200[diff] [blame]5config SOUTHBRIDGE_INTEL_COMMON_RTC
6 def_bool n
Arthur Heymans074730c2019-06-04 14:05:53 +0200[diff] [blame]7
Patrick Rudolph1ae592b2019-03-24 14:41:45 +0100[diff] [blame]8config SOUTHBRIDGE_INTEL_COMMON_PMCLIB
9 def_bool n
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]10 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
11
12config SOUTHBRIDGE_INTEL_COMMON_PMBASE
13 def_bool n
Patrick Rudolph1ae592b2019-03-24 14:41:45 +0100[diff] [blame]14
Patrick Rudolph59de6c92015-12-26 08:33:16 +0100[diff] [blame]15config SOUTHBRIDGE_INTEL_COMMON_GPIO
16 def_bool n
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]17
Angel Ponseef43432021-01-12 22:25:28 +0100[diff] [blame^]18config SOUTHBRIDGE_INTEL_COMMON_HPET
19 def_bool n
20
Angel Pons90e9f542020-06-01 19:31:53 +0200[diff] [blame]21config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
22 def_bool n
23
Arthur Heymans16fe7902017-04-12 17:01:31 +0200[diff] [blame]24config SOUTHBRIDGE_INTEL_COMMON_SMBUS
25 def_bool n
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]26 select HAVE_DEBUG_SMBUS
27
Arthur Heymansbddef0d2017-09-25 12:21:07 +0200[diff] [blame]28config SOUTHBRIDGE_INTEL_COMMON_SPI
29 def_bool n
30 select SPI_FLASH
Arthur Heymans4c804252018-12-03 01:28:18 +0100[diff] [blame]31 select BOOT_DEVICE_SUPPORTS_WRITES
Arthur Heymansbddef0d2017-09-25 12:21:07 +0200[diff] [blame]32
Arthur Heymans47a66032019-10-25 23:43:14 +0200[diff] [blame]33config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7
34 def_bool n
35 select SOUTHBRIDGE_INTEL_COMMON_SPI
36
37config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
38 def_bool n
39 select SOUTHBRIDGE_INTEL_COMMON_SPI
40
41config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
42 def_bool n
43 select SOUTHBRIDGE_INTEL_COMMON_SPI
44
Tobias Diedrich9d8be5a2017-12-13 23:25:32 +0100[diff] [blame]45config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
46 def_bool n
47
48config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
49 def_bool n
50 select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
51
Bill XIEd533b162017-08-22 16:26:22 +0800[diff] [blame]52config HAVE_INTEL_CHIPSET_LOCKDOWN
53 def_bool n
54
Arthur Heymansa0508172018-01-25 11:30:22 +0100[diff] [blame]55config SOUTHBRIDGE_INTEL_COMMON_SMM
56 def_bool n
Nico Huber9faae2b2018-11-14 00:00:35 +0100[diff] [blame]57 select HAVE_POWER_STATE_AFTER_FAILURE
58 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]59 select SOUTHBRIDGE_INTEL_COMMON_PMBASE
Arthur Heymansa0508172018-01-25 11:30:22 +0100[diff] [blame]60
Tristan Corrick167a5122018-10-31 02:28:32 +1300[diff] [blame]61config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
62 bool
63
Tristan Corrick63626b12018-11-30 22:53:50 +1300[diff] [blame]64config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
65 bool
66
Arthur Heymans3457df12019-11-16 10:04:41 +0100[diff] [blame]67config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
68 def_bool n
69 select HAVE_USBDEBUG
70
Stefan Tauneref8b9572018-09-06 00:34:28 +0200[diff] [blame]71config INTEL_DESCRIPTOR_MODE_CAPABLE
72 def_bool n
73 help
74 This config simply states that the platform is *capable* of running in
75 descriptor mode (when the descriptor in flash is valid).
76
Angel Ponsa52016c2018-09-11 13:49:45 +0200[diff] [blame]77config INTEL_DESCRIPTOR_MODE_REQUIRED
78 def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE
79 help
80 This config states descriptor mode is *required* for the platform to
81 function properly, or to function at all.
82
Mathew Kingd8b150f2019-08-09 10:55:37 -0600[diff] [blame]83config VALIDATE_INTEL_DESCRIPTOR
84 depends on INTEL_DESCRIPTOR_MODE_CAPABLE
85 bool "Validate Intel firmware descriptor"
86 default n
87 help
88 This config enables validating the Intel firmware descriptor against the
89 fmap layout. If the firmware descriptor layout does not match the fmap
90 then the bootimage cannot be built.
91
Bill XIEd533b162017-08-22 16:26:22 +0800[diff] [blame]92config INTEL_CHIPSET_LOCKDOWN
93 depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
94 #ChromeOS's payload seems to handle finalization on its on.
95 bool "Lock down chipset in coreboot"
96 default y
97 help
98 Some registers within host bridge on particular chipsets should be
99 locked down on each normal boot path (done by either coreboot or payload)
100 and S3 resume (always done by coreboot). Select this to let coreboot
101 to do this on normal boot path.
Tristan Corrick63626b12018-11-30 22:53:50 +1300[diff] [blame]102
Elyes HAOUAS551a7592019-05-01 16:56:36 +0200[diff] [blame]103config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
104 bool
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]105 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
Angel Ponsb21bffa2020-07-03 01:02:28 +0200[diff] [blame]106
107config FIXED_SMBUS_IO_BASE
108 hex
109 depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
110 default 0x400