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review.coreboot.org / coreboot / 90e9f5472680bbc44fe4e23b390a9323f8c59643 / . / src / southbridge / intel / common / Kconfig
blob: 3030d25757deae7d839dc5d22783f255324baf24 [file] [log] [blame]
Patrick Rudolph45022ae2018-10-01 19:17:11 +0200[diff] [blame]1config SOUTHBRIDGE_INTEL_COMMON_RESET
Arthur Heymans23a6c792019-10-13 22:36:04 +0200[diff] [blame]2 def_bool n
Patrick Rudolph45022ae2018-10-01 19:17:11 +0200[diff] [blame]3 select HAVE_CF9_RESET
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]4
Arthur Heymans074730c2019-06-04 14:05:53 +0200[diff] [blame]5config SOUTHBRIDGE_INTEL_COMMON_RTC
6 def_bool n
Arthur Heymans074730c2019-06-04 14:05:53 +0200[diff] [blame]7
Patrick Rudolph1ae592b2019-03-24 14:41:45 +0100[diff] [blame]8config SOUTHBRIDGE_INTEL_COMMON_PMCLIB
9 def_bool n
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]10 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
11
12config SOUTHBRIDGE_INTEL_COMMON_PMBASE
13 def_bool n
Patrick Rudolph1ae592b2019-03-24 14:41:45 +0100[diff] [blame]14
Patrick Rudolph59de6c92015-12-26 08:33:16 +0100[diff] [blame]15config SOUTHBRIDGE_INTEL_COMMON_GPIO
16 def_bool n
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]17
Angel Pons90e9f542020-06-01 19:31:53 +0200[diff] [blame^]18config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
19 def_bool n
20
Arthur Heymans16fe7902017-04-12 17:01:31 +0200[diff] [blame]21config SOUTHBRIDGE_INTEL_COMMON_SMBUS
22 def_bool n
Kyösti Mälkkib5d998b2017-08-20 21:36:08 +0300[diff] [blame]23 select HAVE_DEBUG_SMBUS
24
Arthur Heymansbddef0d2017-09-25 12:21:07 +0200[diff] [blame]25config SOUTHBRIDGE_INTEL_COMMON_SPI
26 def_bool n
27 select SPI_FLASH
Arthur Heymans4c804252018-12-03 01:28:18 +0100[diff] [blame]28 select BOOT_DEVICE_SUPPORTS_WRITES
Arthur Heymansbddef0d2017-09-25 12:21:07 +0200[diff] [blame]29
Arthur Heymans47a66032019-10-25 23:43:14 +0200[diff] [blame]30config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7
31 def_bool n
32 select SOUTHBRIDGE_INTEL_COMMON_SPI
33
34config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
35 def_bool n
36 select SOUTHBRIDGE_INTEL_COMMON_SPI
37
38config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
39 def_bool n
40 select SOUTHBRIDGE_INTEL_COMMON_SPI
41
Tobias Diedrich9d8be5a2017-12-13 23:25:32 +0100[diff] [blame]42config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
43 def_bool n
44
45config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
46 def_bool n
47 select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
48
Bill XIEd533b162017-08-22 16:26:22 +0800[diff] [blame]49config HAVE_INTEL_CHIPSET_LOCKDOWN
50 def_bool n
51
Arthur Heymansa0508172018-01-25 11:30:22 +0100[diff] [blame]52config SOUTHBRIDGE_INTEL_COMMON_SMM
53 def_bool n
Nico Huber9faae2b2018-11-14 00:00:35 +0100[diff] [blame]54 select HAVE_POWER_STATE_AFTER_FAILURE
55 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]56 select SOUTHBRIDGE_INTEL_COMMON_PMBASE
Arthur Heymansa0508172018-01-25 11:30:22 +0100[diff] [blame]57
Tristan Corrick167a5122018-10-31 02:28:32 +1300[diff] [blame]58config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
59 bool
60
Tristan Corrick63626b12018-11-30 22:53:50 +1300[diff] [blame]61config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
62 bool
63
Arthur Heymans3457df12019-11-16 10:04:41 +0100[diff] [blame]64config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
65 def_bool n
66 select HAVE_USBDEBUG
67
Stefan Tauneref8b9572018-09-06 00:34:28 +0200[diff] [blame]68config INTEL_DESCRIPTOR_MODE_CAPABLE
69 def_bool n
70 help
71 This config simply states that the platform is *capable* of running in
72 descriptor mode (when the descriptor in flash is valid).
73
Angel Ponsa52016c2018-09-11 13:49:45 +0200[diff] [blame]74config INTEL_DESCRIPTOR_MODE_REQUIRED
75 def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE
76 help
77 This config states descriptor mode is *required* for the platform to
78 function properly, or to function at all.
79
Mathew Kingd8b150f2019-08-09 10:55:37 -0600[diff] [blame]80config VALIDATE_INTEL_DESCRIPTOR
81 depends on INTEL_DESCRIPTOR_MODE_CAPABLE
82 bool "Validate Intel firmware descriptor"
83 default n
84 help
85 This config enables validating the Intel firmware descriptor against the
86 fmap layout. If the firmware descriptor layout does not match the fmap
87 then the bootimage cannot be built.
88
Bill XIEd533b162017-08-22 16:26:22 +0800[diff] [blame]89config INTEL_CHIPSET_LOCKDOWN
90 depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
91 #ChromeOS's payload seems to handle finalization on its on.
92 bool "Lock down chipset in coreboot"
93 default y
94 help
95 Some registers within host bridge on particular chipsets should be
96 locked down on each normal boot path (done by either coreboot or payload)
97 and S3 resume (always done by coreboot). Select this to let coreboot
98 to do this on normal boot path.
Tristan Corrick63626b12018-11-30 22:53:50 +1300[diff] [blame]99
Elyes HAOUAS551a7592019-05-01 16:56:36 +0200[diff] [blame]100config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
101 bool
Arthur Heymansb8bda112019-06-04 13:57:47 +0200[diff] [blame]102 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
Angel Ponsb21bffa2020-07-03 01:02:28 +0200[diff] [blame]103
104config FIXED_SMBUS_IO_BASE
105 hex
106 depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
107 default 0x400