| Kyösti Mälkki | 71216c9 | 2013-07-28 23:39:37 +0300 | [diff] [blame] | 1 | config SOUTHBRIDGE_INTEL_COMMON |
| 2 | def_bool n |
| Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 3 | |
| Patrick Rudolph | 59de6c9 | 2015-12-26 08:33:16 +0100 | [diff] [blame] | 4 | config SOUTHBRIDGE_INTEL_COMMON_GPIO |
| 5 | def_bool n |
| Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 6 | |
| Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 7 | config SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| 8 | def_bool n |
| Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 9 | select HAVE_DEBUG_SMBUS |
| 10 | |
| Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 11 | config SOUTHBRIDGE_INTEL_COMMON_SPI |
| 12 | def_bool n |
| 13 | select SPI_FLASH |
| 14 | |
| Tobias Diedrich | 9d8be5a | 2017-12-13 23:25:32 +0100 | [diff] [blame] | 15 | config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 16 | def_bool n |
| 17 | |
| 18 | config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
| 19 | def_bool n |
| 20 | select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 21 | |
| Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 22 | config HAVE_INTEL_CHIPSET_LOCKDOWN |
| 23 | def_bool n |
| 24 | |
| Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame^] | 25 | config SOUTHBRIDGE_INTEL_COMMON_SMM |
| 26 | def_bool n |
| 27 | |
| Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 28 | config INTEL_CHIPSET_LOCKDOWN |
| 29 | depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS |
| 30 | #ChromeOS's payload seems to handle finalization on its on. |
| 31 | bool "Lock down chipset in coreboot" |
| 32 | default y |
| 33 | help |
| 34 | Some registers within host bridge on particular chipsets should be |
| 35 | locked down on each normal boot path (done by either coreboot or payload) |
| 36 | and S3 resume (always done by coreboot). Select this to let coreboot |
| 37 | to do this on normal boot path. |