Kyösti Mälkki | 71216c9 | 2013-07-28 23:39:37 +0300 | [diff] [blame] | 1 | config SOUTHBRIDGE_INTEL_COMMON |
| 2 | def_bool n |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 3 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
| 4 | |
| 5 | config SOUTHBRIDGE_INTEL_COMMON_RESET |
| 6 | bool |
| 7 | select HAVE_CF9_RESET |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 8 | |
Patrick Rudolph | 1ae592b | 2019-03-24 14:41:45 +0100 | [diff] [blame] | 9 | config SOUTHBRIDGE_INTEL_COMMON_PMCLIB |
| 10 | def_bool n |
| 11 | depends on SOUTHBRIDGE_INTEL_COMMON |
Arthur Heymans | b8bda11 | 2019-06-04 13:57:47 +0200 | [diff] [blame^] | 12 | depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE |
| 13 | |
| 14 | config SOUTHBRIDGE_INTEL_COMMON_PMBASE |
| 15 | def_bool n |
| 16 | depends on SOUTHBRIDGE_INTEL_COMMON |
Patrick Rudolph | 1ae592b | 2019-03-24 14:41:45 +0100 | [diff] [blame] | 17 | |
Patrick Rudolph | 59de6c9 | 2015-12-26 08:33:16 +0100 | [diff] [blame] | 18 | config SOUTHBRIDGE_INTEL_COMMON_GPIO |
| 19 | def_bool n |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 20 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 21 | config SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| 22 | def_bool n |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 23 | select HAVE_DEBUG_SMBUS |
| 24 | |
Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 25 | config SOUTHBRIDGE_INTEL_COMMON_SPI |
| 26 | def_bool n |
| 27 | select SPI_FLASH |
Arthur Heymans | 4c80425 | 2018-12-03 01:28:18 +0100 | [diff] [blame] | 28 | select BOOT_DEVICE_SUPPORTS_WRITES |
Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 29 | |
Tobias Diedrich | 9d8be5a | 2017-12-13 23:25:32 +0100 | [diff] [blame] | 30 | config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 31 | def_bool n |
| 32 | |
| 33 | config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
| 34 | def_bool n |
| 35 | select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 36 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 37 | config HAVE_INTEL_CHIPSET_LOCKDOWN |
| 38 | def_bool n |
| 39 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 40 | config SOUTHBRIDGE_INTEL_COMMON_SMM |
| 41 | def_bool n |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 42 | select HAVE_POWER_STATE_AFTER_FAILURE |
| 43 | select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
Arthur Heymans | b8bda11 | 2019-06-04 13:57:47 +0200 | [diff] [blame^] | 44 | select SOUTHBRIDGE_INTEL_COMMON_PMBASE |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 45 | |
Tristan Corrick | 167a512 | 2018-10-31 02:28:32 +1300 | [diff] [blame] | 46 | config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT |
| 47 | bool |
| 48 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 49 | config SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
| 50 | bool |
| 51 | |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 52 | config INTEL_DESCRIPTOR_MODE_CAPABLE |
| 53 | def_bool n |
| 54 | help |
| 55 | This config simply states that the platform is *capable* of running in |
| 56 | descriptor mode (when the descriptor in flash is valid). |
| 57 | |
Angel Pons | a52016c | 2018-09-11 13:49:45 +0200 | [diff] [blame] | 58 | config INTEL_DESCRIPTOR_MODE_REQUIRED |
| 59 | def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE |
| 60 | help |
| 61 | This config states descriptor mode is *required* for the platform to |
| 62 | function properly, or to function at all. |
| 63 | |
Mathew King | d8b150f | 2019-08-09 10:55:37 -0600 | [diff] [blame] | 64 | config VALIDATE_INTEL_DESCRIPTOR |
| 65 | depends on INTEL_DESCRIPTOR_MODE_CAPABLE |
| 66 | bool "Validate Intel firmware descriptor" |
| 67 | default n |
| 68 | help |
| 69 | This config enables validating the Intel firmware descriptor against the |
| 70 | fmap layout. If the firmware descriptor layout does not match the fmap |
| 71 | then the bootimage cannot be built. |
| 72 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 73 | config INTEL_CHIPSET_LOCKDOWN |
| 74 | depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS |
| 75 | #ChromeOS's payload seems to handle finalization on its on. |
| 76 | bool "Lock down chipset in coreboot" |
| 77 | default y |
| 78 | help |
| 79 | Some registers within host bridge on particular chipsets should be |
| 80 | locked down on each normal boot path (done by either coreboot or payload) |
| 81 | and S3 resume (always done by coreboot). Select this to let coreboot |
| 82 | to do this on normal boot path. |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 83 | |
Elyes HAOUAS | 551a759 | 2019-05-01 16:56:36 +0200 | [diff] [blame] | 84 | config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG |
| 85 | bool |
| 86 | depends on SOUTHBRIDGE_INTEL_COMMON |
Arthur Heymans | b8bda11 | 2019-06-04 13:57:47 +0200 | [diff] [blame^] | 87 | depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE |
Elyes HAOUAS | 551a759 | 2019-05-01 16:56:36 +0200 | [diff] [blame] | 88 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 89 | if SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
| 90 | |
| 91 | choice |
| 92 | prompt "Flash locking during chipset lockdown" |
| 93 | default LOCK_SPI_FLASH_NONE |
| 94 | |
| 95 | config LOCK_SPI_FLASH_NONE |
| 96 | bool "Don't lock flash sections" |
| 97 | |
| 98 | config LOCK_SPI_FLASH_RO |
| 99 | bool "Write-protect all flash sections" |
| 100 | help |
| 101 | Select this if you want to write-protect the whole firmware flash |
| 102 | chip. The locking will take place during the chipset lockdown, which |
| 103 | is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) |
| 104 | or has to be triggered later (e.g. by the payload or the OS). |
| 105 | |
| 106 | NOTE: If you trigger the chipset lockdown unconditionally, |
| 107 | you won't be able to write to the flash chip using the |
| 108 | internal programmer any more. |
| 109 | |
| 110 | config LOCK_SPI_FLASH_NO_ACCESS |
| 111 | bool "Write-protect all flash sections and read-protect non-BIOS sections" |
| 112 | help |
| 113 | Select this if you want to protect the firmware flash against all |
| 114 | further accesses (with the exception of the memory mapped BIOS re- |
| 115 | gion which is always readable). The locking will take place during |
| 116 | the chipset lockdown, which is either triggered by coreboot (when |
| 117 | INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. |
| 118 | by the payload or the OS). |
| 119 | |
| 120 | NOTE: If you trigger the chipset lockdown unconditionally, |
| 121 | you won't be able to write to the flash chip using the |
| 122 | internal programmer any more. |
| 123 | |
| 124 | endchoice |
| 125 | |
| 126 | endif |