Kyösti Mälkki | 71216c9 | 2013-07-28 23:39:37 +0300 | [diff] [blame] | 1 | config SOUTHBRIDGE_INTEL_COMMON |
| 2 | def_bool n |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 3 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
| 4 | |
| 5 | config SOUTHBRIDGE_INTEL_COMMON_RESET |
| 6 | bool |
| 7 | select HAVE_CF9_RESET |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 8 | |
Patrick Rudolph | 1ae592b | 2019-03-24 14:41:45 +0100 | [diff] [blame^] | 9 | config SOUTHBRIDGE_INTEL_COMMON_PMCLIB |
| 10 | def_bool n |
| 11 | depends on SOUTHBRIDGE_INTEL_COMMON |
| 12 | |
Patrick Rudolph | 59de6c9 | 2015-12-26 08:33:16 +0100 | [diff] [blame] | 13 | config SOUTHBRIDGE_INTEL_COMMON_GPIO |
| 14 | def_bool n |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 15 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 16 | config SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| 17 | def_bool n |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 18 | select HAVE_DEBUG_SMBUS |
| 19 | |
Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 20 | config SOUTHBRIDGE_INTEL_COMMON_SPI |
| 21 | def_bool n |
| 22 | select SPI_FLASH |
| 23 | |
Tobias Diedrich | 9d8be5a | 2017-12-13 23:25:32 +0100 | [diff] [blame] | 24 | config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 25 | def_bool n |
| 26 | |
| 27 | config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
| 28 | def_bool n |
| 29 | select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 30 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 31 | config HAVE_INTEL_CHIPSET_LOCKDOWN |
| 32 | def_bool n |
| 33 | |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 34 | config SOUTHBRIDGE_INTEL_COMMON_SMM |
| 35 | def_bool n |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 36 | select HAVE_POWER_STATE_AFTER_FAILURE |
| 37 | select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 38 | |
Tristan Corrick | 167a512 | 2018-10-31 02:28:32 +1300 | [diff] [blame] | 39 | config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT |
| 40 | bool |
| 41 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 42 | config SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
| 43 | bool |
| 44 | |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 45 | config INTEL_DESCRIPTOR_MODE_CAPABLE |
| 46 | def_bool n |
| 47 | help |
| 48 | This config simply states that the platform is *capable* of running in |
| 49 | descriptor mode (when the descriptor in flash is valid). |
| 50 | |
Angel Pons | a52016c | 2018-09-11 13:49:45 +0200 | [diff] [blame] | 51 | config INTEL_DESCRIPTOR_MODE_REQUIRED |
| 52 | def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE |
| 53 | help |
| 54 | This config states descriptor mode is *required* for the platform to |
| 55 | function properly, or to function at all. |
| 56 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 57 | config INTEL_CHIPSET_LOCKDOWN |
| 58 | depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS |
| 59 | #ChromeOS's payload seems to handle finalization on its on. |
| 60 | bool "Lock down chipset in coreboot" |
| 61 | default y |
| 62 | help |
| 63 | Some registers within host bridge on particular chipsets should be |
| 64 | locked down on each normal boot path (done by either coreboot or payload) |
| 65 | and S3 resume (always done by coreboot). Select this to let coreboot |
| 66 | to do this on normal boot path. |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 67 | |
| 68 | if SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
| 69 | |
| 70 | choice |
| 71 | prompt "Flash locking during chipset lockdown" |
| 72 | default LOCK_SPI_FLASH_NONE |
| 73 | |
| 74 | config LOCK_SPI_FLASH_NONE |
| 75 | bool "Don't lock flash sections" |
| 76 | |
| 77 | config LOCK_SPI_FLASH_RO |
| 78 | bool "Write-protect all flash sections" |
| 79 | help |
| 80 | Select this if you want to write-protect the whole firmware flash |
| 81 | chip. The locking will take place during the chipset lockdown, which |
| 82 | is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) |
| 83 | or has to be triggered later (e.g. by the payload or the OS). |
| 84 | |
| 85 | NOTE: If you trigger the chipset lockdown unconditionally, |
| 86 | you won't be able to write to the flash chip using the |
| 87 | internal programmer any more. |
| 88 | |
| 89 | config LOCK_SPI_FLASH_NO_ACCESS |
| 90 | bool "Write-protect all flash sections and read-protect non-BIOS sections" |
| 91 | help |
| 92 | Select this if you want to protect the firmware flash against all |
| 93 | further accesses (with the exception of the memory mapped BIOS re- |
| 94 | gion which is always readable). The locking will take place during |
| 95 | the chipset lockdown, which is either triggered by coreboot (when |
| 96 | INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. |
| 97 | by the payload or the OS). |
| 98 | |
| 99 | NOTE: If you trigger the chipset lockdown unconditionally, |
| 100 | you won't be able to write to the flash chip using the |
| 101 | internal programmer any more. |
| 102 | |
| 103 | endchoice |
| 104 | |
| 105 | endif |