| Kyösti Mälkki | 71216c9 | 2013-07-28 23:39:37 +0300 | [diff] [blame] | 1 | config SOUTHBRIDGE_INTEL_COMMON |
| 2 | def_bool n |
| Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 3 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
| 4 | |
| 5 | config SOUTHBRIDGE_INTEL_COMMON_RESET |
| 6 | bool |
| 7 | select HAVE_CF9_RESET |
| Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 8 | |
| Patrick Rudolph | 59de6c9 | 2015-12-26 08:33:16 +0100 | [diff] [blame] | 9 | config SOUTHBRIDGE_INTEL_COMMON_GPIO |
| 10 | def_bool n |
| Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 11 | |
| Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 12 | config SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| 13 | def_bool n |
| Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 14 | select HAVE_DEBUG_SMBUS |
| 15 | |
| Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 16 | config SOUTHBRIDGE_INTEL_COMMON_SPI |
| 17 | def_bool n |
| 18 | select SPI_FLASH |
| 19 | |
| Tobias Diedrich | 9d8be5a | 2017-12-13 23:25:32 +0100 | [diff] [blame] | 20 | config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 21 | def_bool n |
| 22 | |
| 23 | config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
| 24 | def_bool n |
| 25 | select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN |
| 26 | |
| Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 27 | config HAVE_INTEL_CHIPSET_LOCKDOWN |
| 28 | def_bool n |
| 29 | |
| Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 30 | config SOUTHBRIDGE_INTEL_COMMON_SMM |
| 31 | def_bool n |
| 32 | |
| Tristan Corrick | 167a512 | 2018-10-31 02:28:32 +1300 | [diff] [blame^] | 33 | config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT |
| 34 | bool |
| 35 | |
| Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 36 | config INTEL_DESCRIPTOR_MODE_CAPABLE |
| 37 | def_bool n |
| 38 | help |
| 39 | This config simply states that the platform is *capable* of running in |
| 40 | descriptor mode (when the descriptor in flash is valid). |
| 41 | |
| Angel Pons | a52016c | 2018-09-11 13:49:45 +0200 | [diff] [blame] | 42 | config INTEL_DESCRIPTOR_MODE_REQUIRED |
| 43 | def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE |
| 44 | help |
| 45 | This config states descriptor mode is *required* for the platform to |
| 46 | function properly, or to function at all. |
| 47 | |
| Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 48 | config INTEL_CHIPSET_LOCKDOWN |
| 49 | depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS |
| 50 | #ChromeOS's payload seems to handle finalization on its on. |
| 51 | bool "Lock down chipset in coreboot" |
| 52 | default y |
| 53 | help |
| 54 | Some registers within host bridge on particular chipsets should be |
| 55 | locked down on each normal boot path (done by either coreboot or payload) |
| 56 | and S3 resume (always done by coreboot). Select this to let coreboot |
| 57 | to do this on normal boot path. |