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Stefan Reinauer155e9b52012-04-27 23:19:58 +02001chip northbridge/intel/sandybridge
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01002 # IGD Displays
3 register "gfx.ndid" = "3"
4 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Stefan Reinauer155e9b52012-04-27 23:19:58 +02005
6 # Enable DisplayPort Hotplug with 6ms pulse
7 register "gpu_dp_d_hotplug" = "0x06"
8
9 # Enable Panel as LVDS and configure power delays
10 register "gpu_panel_port_select" = "0" # LVDS
11 register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
12 register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
13 register "gpu_panel_power_down_delay" = "150" # T3: 15ms
14 register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
15 register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
16
Matt DeVilliereaea9c92018-12-31 15:07:42 -060017 # Set backlight PWM values
18 register "gpu_cpu_backlight" = "0x000001e8"
19 register "gpu_pch_backlight" = "0x03d00000"
20
Vladimir Serbinenko0a07c5c2016-02-10 03:01:37 +010021 register "max_mem_clock_mhz" = "666"
22
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080023 device cpu_cluster 0 on
Stefan Reinauer155e9b52012-04-27 23:19:58 +020024 chip cpu/intel/socket_rPGA989
25 device lapic 0 on end
26 end
27 chip cpu/intel/model_206ax
28 # Magic APIC ID to locate this chip
29 device lapic 0xACAC off end
30
Stefan Reinauer155e9b52012-04-27 23:19:58 +020031 register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
32 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
33 register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
34
35 register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
36 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
37 register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
38 end
39 end
40
Patrick Rudolph266a1f72016-06-09 18:13:34 +020041 register "pci_mmio_size" = "1024"
42
Stefan Reinauer4aff4452013-02-12 14:17:15 -080043 device domain 0 on
Sven Schnelle5be20602012-08-20 11:21:00 +020044 ioapic_irq 4 INTA 0x10
45 ioapic_irq 4 INTB 0x11
46 ioapic_irq 4 INTC 0x12
47 ioapic_irq 4 INTD 0x13
Stefan Reinauer56c7dc72012-05-15 12:36:57 -070048 subsystemid 0x1ae0 0xc000 inherit
Stefan Reinauer155e9b52012-04-27 23:19:58 +020049 device pci 00.0 on end # host bridge
50 device pci 02.0 on end # vga controller
51
52 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
Stefan Reinauer155e9b52012-04-27 23:19:58 +020053 # GPI routing
54 # 0 No effect (default)
55 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
56 # 2 SCI (if corresponding GPIO_EN bit is also set)
57 register "alt_gp_smi_en" = "0x0002"
58 register "gpi1_routing" = "1"
59 register "gpi7_routing" = "2"
60
Stefan Reinauer155e9b52012-04-27 23:19:58 +020061 register "sata_port_map" = "0x1"
62
63 # EC range is 0xa00-0xa3f
64 register "gen1_dec" = "0x003c0a01"
65 register "gen2_dec" = "0x003c0b01"
66
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020067 register "c2_latency" = "1"
68 register "p_cnt_throttling_supported" = "0"
69
Stefan Reinauer155e9b52012-04-27 23:19:58 +020070 device pci 16.0 on end # Management Engine Interface 1
71 device pci 16.1 off end # Management Engine Interface 2
72 device pci 16.2 off end # Management Engine IDE-R
73 device pci 16.3 off end # Management Engine KT
74 device pci 19.0 off end # Intel Gigabit Ethernet
Sven Schnelle5be20602012-08-20 11:21:00 +020075 device pci 1a.0 on # USB2 EHCI #2
76 ioapic_irq 4 INTA 0x11
77 end
78 device pci 1b.0 on # High Definition Audio
79 ioapic_irq 4 INTA 0x16
80 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020081 device pci 1c.0 on end # PCIe Port #1 (WLAN)
82 device pci 1c.1 off end # PCIe Port #2
83 device pci 1c.2 off end # PCIe Port #3
Sven Schnelle5be20602012-08-20 11:21:00 +020084 device pci 1c.3 on # PCIe Port #4 (LAN)
85 # ioapic_irq 4 INTA 0x13
86 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020087 device pci 1c.4 off end # PCIe Port #5
88 device pci 1c.5 off end # PCIe Port #6
89 device pci 1c.6 off end # PCIe Port #7
90 device pci 1c.7 off end # PCIe Port #8
Sven Schnelle5be20602012-08-20 11:21:00 +020091 device pci 1d.0 on # USB2 EHCI #1
92 ioapic_irq 4 INTA 0x13
93 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020094 device pci 1e.0 off end # PCI bridge
95 device pci 1f.0 on # LPC bridge
Sven Schnelle5be20602012-08-20 11:21:00 +020096 ioapic_irq 4 INTA 0x10
Stefan Reinauer155e9b52012-04-27 23:19:58 +020097 chip superio/smsc/mec1308
98 device pnp 2e.1 on # PM1
99 io 0x60 = 0xb00
100 end
101 device pnp 2e.2 off end # EC1
102 device pnp 2e.3 off end # EC2
103 device pnp 2e.4 off end # UART
104 device pnp 2e.7 on # KBC
105 irq 0x70 = 1
106 end
107 device pnp 2e.8 on # EC0
108 io 0x60 = 0x62
109 end
110 device pnp 2e.9 on # MBX
111 io 0x60 = 0xa00
112 end
113 end
114 chip ec/smsc/mec1308
115 register "mailbox_port" = "0xa00"
116 device pnp ff.1 off end
117 end
Sven Schnelle5be20602012-08-20 11:21:00 +0200118
119 chip drivers/generic/ioapic
120 register "have_isa_interrupts" = "1"
121 register "irq_on_fsb" = "1"
122 register "enable_virtual_wire" = "1"
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800123 register "base" = "(void *)0xfec00000"
Sven Schnelle5be20602012-08-20 11:21:00 +0200124 device ioapic 4 on end
125 end
Matt DeVillier3044af72018-08-01 13:05:14 -0500126 chip drivers/pc80/tpm
127 device pnp 0c31.0 on end
128 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +0200129 end
Sven Schnelle5be20602012-08-20 11:21:00 +0200130 device pci 1f.2 on # SATA Controller 1
131 ioapic_irq 4 INTA 0x10
132 end
133 device pci 1f.3 on # SMBus
134 ioapic_irq 4 INTC 0x17
135 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +0200136 device pci 1f.5 off end # SATA Controller 2
137 device pci 1f.6 on end # Thermal
138 end
139 end
140end