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Stefan Reinauer155e9b52012-04-27 23:19:58 +02001chip northbridge/intel/sandybridge
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01002 # IGD Displays
3 register "gfx.ndid" = "3"
4 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Stefan Reinauer155e9b52012-04-27 23:19:58 +02005
6 # Enable DisplayPort Hotplug with 6ms pulse
7 register "gpu_dp_d_hotplug" = "0x06"
8
9 # Enable Panel as LVDS and configure power delays
10 register "gpu_panel_port_select" = "0" # LVDS
11 register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
12 register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
13 register "gpu_panel_power_down_delay" = "150" # T3: 15ms
14 register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
15 register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
16
Vladimir Serbinenko0a07c5c2016-02-10 03:01:37 +010017 register "max_mem_clock_mhz" = "666"
18
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080019 device cpu_cluster 0 on
Stefan Reinauer155e9b52012-04-27 23:19:58 +020020 chip cpu/intel/socket_rPGA989
21 device lapic 0 on end
22 end
23 chip cpu/intel/model_206ax
24 # Magic APIC ID to locate this chip
25 device lapic 0xACAC off end
26
Stefan Reinauer155e9b52012-04-27 23:19:58 +020027 register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
28 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
29 register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
30
31 register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
32 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
33 register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
34 end
35 end
36
Patrick Rudolph266a1f72016-06-09 18:13:34 +020037 register "pci_mmio_size" = "1024"
38
Stefan Reinauer4aff4452013-02-12 14:17:15 -080039 device domain 0 on
Sven Schnelle5be20602012-08-20 11:21:00 +020040 ioapic_irq 4 INTA 0x10
41 ioapic_irq 4 INTB 0x11
42 ioapic_irq 4 INTC 0x12
43 ioapic_irq 4 INTD 0x13
Stefan Reinauer56c7dc72012-05-15 12:36:57 -070044 subsystemid 0x1ae0 0xc000 inherit
Stefan Reinauer155e9b52012-04-27 23:19:58 +020045 device pci 00.0 on end # host bridge
46 device pci 02.0 on end # vga controller
47
48 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
Stefan Reinauer155e9b52012-04-27 23:19:58 +020049 # GPI routing
50 # 0 No effect (default)
51 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
52 # 2 SCI (if corresponding GPIO_EN bit is also set)
53 register "alt_gp_smi_en" = "0x0002"
54 register "gpi1_routing" = "1"
55 register "gpi7_routing" = "2"
56
Stefan Reinauer155e9b52012-04-27 23:19:58 +020057 register "sata_port_map" = "0x1"
58
59 # EC range is 0xa00-0xa3f
60 register "gen1_dec" = "0x003c0a01"
61 register "gen2_dec" = "0x003c0b01"
62
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020063 register "c2_latency" = "1"
64 register "p_cnt_throttling_supported" = "0"
65
Stefan Reinauer155e9b52012-04-27 23:19:58 +020066 device pci 16.0 on end # Management Engine Interface 1
67 device pci 16.1 off end # Management Engine Interface 2
68 device pci 16.2 off end # Management Engine IDE-R
69 device pci 16.3 off end # Management Engine KT
70 device pci 19.0 off end # Intel Gigabit Ethernet
Sven Schnelle5be20602012-08-20 11:21:00 +020071 device pci 1a.0 on # USB2 EHCI #2
72 ioapic_irq 4 INTA 0x11
73 end
74 device pci 1b.0 on # High Definition Audio
75 ioapic_irq 4 INTA 0x16
76 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020077 device pci 1c.0 on end # PCIe Port #1 (WLAN)
78 device pci 1c.1 off end # PCIe Port #2
79 device pci 1c.2 off end # PCIe Port #3
Sven Schnelle5be20602012-08-20 11:21:00 +020080 device pci 1c.3 on # PCIe Port #4 (LAN)
81 # ioapic_irq 4 INTA 0x13
82 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020083 device pci 1c.4 off end # PCIe Port #5
84 device pci 1c.5 off end # PCIe Port #6
85 device pci 1c.6 off end # PCIe Port #7
86 device pci 1c.7 off end # PCIe Port #8
Sven Schnelle5be20602012-08-20 11:21:00 +020087 device pci 1d.0 on # USB2 EHCI #1
88 ioapic_irq 4 INTA 0x13
89 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020090 device pci 1e.0 off end # PCI bridge
91 device pci 1f.0 on # LPC bridge
Sven Schnelle5be20602012-08-20 11:21:00 +020092 ioapic_irq 4 INTA 0x10
Stefan Reinauer155e9b52012-04-27 23:19:58 +020093 chip superio/smsc/mec1308
94 device pnp 2e.1 on # PM1
95 io 0x60 = 0xb00
96 end
97 device pnp 2e.2 off end # EC1
98 device pnp 2e.3 off end # EC2
99 device pnp 2e.4 off end # UART
100 device pnp 2e.7 on # KBC
101 irq 0x70 = 1
102 end
103 device pnp 2e.8 on # EC0
104 io 0x60 = 0x62
105 end
106 device pnp 2e.9 on # MBX
107 io 0x60 = 0xa00
108 end
109 end
110 chip ec/smsc/mec1308
111 register "mailbox_port" = "0xa00"
112 device pnp ff.1 off end
113 end
Sven Schnelle5be20602012-08-20 11:21:00 +0200114
115 chip drivers/generic/ioapic
116 register "have_isa_interrupts" = "1"
117 register "irq_on_fsb" = "1"
118 register "enable_virtual_wire" = "1"
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800119 register "base" = "(void *)0xfec00000"
Sven Schnelle5be20602012-08-20 11:21:00 +0200120 device ioapic 4 on end
121 end
Matt DeVillier3044af72018-08-01 13:05:14 -0500122 chip drivers/pc80/tpm
123 device pnp 0c31.0 on end
124 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +0200125 end
Sven Schnelle5be20602012-08-20 11:21:00 +0200126 device pci 1f.2 on # SATA Controller 1
127 ioapic_irq 4 INTA 0x10
128 end
129 device pci 1f.3 on # SMBus
130 ioapic_irq 4 INTC 0x17
131 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +0200132 device pci 1f.5 off end # SATA Controller 2
133 device pci 1f.6 on end # Thermal
134 end
135 end
136end