blob: c2f091d4390853725e4fb4d633b49a59168497ea [file] [log] [blame]
Stefan Reinauer155e9b52012-04-27 23:19:58 +02001chip northbridge/intel/sandybridge
2
3 # Enable DisplayPort Hotplug with 6ms pulse
4 register "gpu_dp_d_hotplug" = "0x06"
5
6 # Enable Panel as LVDS and configure power delays
7 register "gpu_panel_port_select" = "0" # LVDS
8 register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
9 register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
10 register "gpu_panel_power_down_delay" = "150" # T3: 15ms
11 register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
12 register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
13
14 device lapic_cluster 0 on
15 chip cpu/intel/socket_rPGA989
16 device lapic 0 on end
17 end
18 chip cpu/intel/model_206ax
19 # Magic APIC ID to locate this chip
20 device lapic 0xACAC off end
21
22 # Coordinate with HW_ALL
23 register "pstate_coord_type" = "0xfe"
24
25 register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
26 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
27 register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
28
29 register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
30 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
31 register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
32 end
33 end
34
Stefan Reinauer4aff4452013-02-12 14:17:15 -080035 device domain 0 on
Sven Schnelle5be20602012-08-20 11:21:00 +020036 ioapic_irq 4 INTA 0x10
37 ioapic_irq 4 INTB 0x11
38 ioapic_irq 4 INTC 0x12
39 ioapic_irq 4 INTD 0x13
Stefan Reinauer56c7dc72012-05-15 12:36:57 -070040 subsystemid 0x1ae0 0xc000 inherit
Stefan Reinauer155e9b52012-04-27 23:19:58 +020041 device pci 00.0 on end # host bridge
42 device pci 02.0 on end # vga controller
43
44 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
45 register "pirqa_routing" = "0x8b"
46 register "pirqb_routing" = "0x8a"
47 register "pirqc_routing" = "0x8b"
48 register "pirqd_routing" = "0x8b"
49 register "pirqe_routing" = "0x80"
50 register "pirqf_routing" = "0x80"
51 register "pirqg_routing" = "0x80"
52 register "pirqh_routing" = "0x80"
53
54 # GPI routing
55 # 0 No effect (default)
56 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
57 # 2 SCI (if corresponding GPIO_EN bit is also set)
58 register "alt_gp_smi_en" = "0x0002"
59 register "gpi1_routing" = "1"
60 register "gpi7_routing" = "2"
61
62 register "ide_legacy_combined" = "0x0"
63 register "sata_ahci" = "0x1"
64 register "sata_port_map" = "0x1"
65
66 # EC range is 0xa00-0xa3f
67 register "gen1_dec" = "0x003c0a01"
68 register "gen2_dec" = "0x003c0b01"
69
70 device pci 16.0 on end # Management Engine Interface 1
71 device pci 16.1 off end # Management Engine Interface 2
72 device pci 16.2 off end # Management Engine IDE-R
73 device pci 16.3 off end # Management Engine KT
74 device pci 19.0 off end # Intel Gigabit Ethernet
Sven Schnelle5be20602012-08-20 11:21:00 +020075 device pci 1a.0 on # USB2 EHCI #2
76 ioapic_irq 4 INTA 0x11
77 end
78 device pci 1b.0 on # High Definition Audio
79 ioapic_irq 4 INTA 0x16
80 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020081 device pci 1c.0 on end # PCIe Port #1 (WLAN)
82 device pci 1c.1 off end # PCIe Port #2
83 device pci 1c.2 off end # PCIe Port #3
Sven Schnelle5be20602012-08-20 11:21:00 +020084 device pci 1c.3 on # PCIe Port #4 (LAN)
85 # ioapic_irq 4 INTA 0x13
86 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020087 device pci 1c.4 off end # PCIe Port #5
88 device pci 1c.5 off end # PCIe Port #6
89 device pci 1c.6 off end # PCIe Port #7
90 device pci 1c.7 off end # PCIe Port #8
Sven Schnelle5be20602012-08-20 11:21:00 +020091 device pci 1d.0 on # USB2 EHCI #1
92 ioapic_irq 4 INTA 0x13
93 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +020094 device pci 1e.0 off end # PCI bridge
95 device pci 1f.0 on # LPC bridge
Sven Schnelle5be20602012-08-20 11:21:00 +020096 ioapic_irq 4 INTA 0x10
Stefan Reinauer155e9b52012-04-27 23:19:58 +020097 chip superio/smsc/mec1308
98 device pnp 2e.1 on # PM1
99 io 0x60 = 0xb00
100 end
101 device pnp 2e.2 off end # EC1
102 device pnp 2e.3 off end # EC2
103 device pnp 2e.4 off end # UART
104 device pnp 2e.7 on # KBC
105 irq 0x70 = 1
106 end
107 device pnp 2e.8 on # EC0
108 io 0x60 = 0x62
109 end
110 device pnp 2e.9 on # MBX
111 io 0x60 = 0xa00
112 end
113 end
114 chip ec/smsc/mec1308
115 register "mailbox_port" = "0xa00"
116 device pnp ff.1 off end
117 end
Sven Schnelle5be20602012-08-20 11:21:00 +0200118
119 chip drivers/generic/ioapic
120 register "have_isa_interrupts" = "1"
121 register "irq_on_fsb" = "1"
122 register "enable_virtual_wire" = "1"
123 register "base" = "0xfec00000"
124 device ioapic 4 on end
125 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +0200126 end
Sven Schnelle5be20602012-08-20 11:21:00 +0200127 device pci 1f.2 on # SATA Controller 1
128 ioapic_irq 4 INTA 0x10
129 end
130 device pci 1f.3 on # SMBus
131 ioapic_irq 4 INTC 0x17
132 end
Stefan Reinauer155e9b52012-04-27 23:19:58 +0200133 device pci 1f.5 off end # SATA Controller 2
134 device pci 1f.6 on end # Thermal
135 end
136 end
137end