efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 14 | */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 15 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 16 | /****************************************************************************** |
| 17 | * AMD Generic Encapsulated Software Architecture |
| 18 | * |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 19 | * $Workfile:: cache_as_ram.S |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 20 | * |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 21 | * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 22 | * |
| 23 | ****************************************************************************** |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 24 | */ |
| 25 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 26 | #include "gcccar.inc" |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 27 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 28 | #include <cpu/x86/post_code.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 29 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 30 | .code32 |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 31 | .globl _cache_as_ram_setup, _cache_as_ram_setup_end |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 32 | .globl chipset_teardown_car |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 33 | |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 34 | _cache_as_ram_setup: |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 35 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 36 | /* Preserve BIST. */ |
| 37 | movd %eax, %mm0 |
Kyösti Mälkki | 1779d53 | 2016-11-23 21:29:26 +0200 | [diff] [blame] | 38 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 39 | post_code(0xa0) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 40 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 41 | /* enable SSE2 128bit instructions */ |
| 42 | /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 43 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 44 | movl %cr4, %eax |
| 45 | orl $(3 << 9), %eax |
| 46 | movl %eax, %cr4 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 47 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 48 | post_code(0xa1) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 49 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 50 | AMD_ENABLE_STACK |
Kyösti Mälkki | f6fe2f1 | 2016-11-21 11:26:48 +0200 | [diff] [blame] | 51 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 52 | /* Align the stack. */ |
| 53 | and $0xFFFFFFF0, %esp |
Kyösti Mälkki | 26929bd | 2016-11-23 20:40:53 +0200 | [diff] [blame] | 54 | |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 55 | #ifdef __x86_64__ |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 56 | /* switch to 64 bit long mode */ |
| 57 | mov %esi, %ecx |
| 58 | add $0, %ecx # core number |
| 59 | xor %eax, %eax |
| 60 | lea (0x1000+0x23)(%ecx), %edi |
| 61 | mov %edi, (%ecx) |
| 62 | mov %eax, 4(%ecx) |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 63 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 64 | lea 0x1000(%ecx), %edi |
| 65 | movl $0x000000e3, 0x00(%edi) |
| 66 | movl %eax, 0x04(%edi) |
| 67 | movl $0x400000e3, 0x08(%edi) |
| 68 | movl %eax, 0x0c(%edi) |
| 69 | movl $0x800000e3, 0x10(%edi) |
| 70 | movl %eax, 0x14(%edi) |
| 71 | movl $0xc00000e3, 0x18(%edi) |
| 72 | movl %eax, 0x1c(%edi) |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 73 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 74 | # load ROM based identity mapped page tables |
| 75 | mov %ecx, %eax |
| 76 | mov %eax, %cr3 |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 77 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 78 | # enable PAE |
| 79 | mov %cr4, %eax |
| 80 | bts $5, %eax |
| 81 | mov %eax, %cr4 |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 82 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 83 | # enable long mode |
| 84 | mov $0xC0000080, %ecx |
| 85 | rdmsr |
| 86 | bts $8, %eax |
| 87 | wrmsr |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 88 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 89 | # enable paging |
| 90 | mov %cr0, %eax |
| 91 | bts $31, %eax |
| 92 | mov %eax, %cr0 |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 93 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 94 | # use call far to switch to 64-bit code segment |
| 95 | ljmp $0x18, $1f |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 96 | 1: |
Kyösti Mälkki | 13cf135 | 2016-11-21 07:37:13 +0200 | [diff] [blame] | 97 | |
Kyösti Mälkki | df7ff31 | 2016-11-25 12:02:00 +0200 | [diff] [blame] | 98 | #endif |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 99 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 100 | call early_all_cores |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 101 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 102 | /* Must maintain 16-byte stack alignment here. */ |
| 103 | pushl $0x0 |
| 104 | pushl $0x0 |
| 105 | pushl $0x0 |
| 106 | movd %mm0, %eax /* bist */ |
| 107 | pushl %eax |
| 108 | call romstage_main |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 109 | |
| 110 | #if IS_ENABLED(CONFIG_POSTCAR_STAGE) |
| 111 | |
| 112 | /* We do not return. Execution continues with run_postcar_phase() |
| 113 | * calling to chipset_teardown_car below. |
| 114 | */ |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 115 | jmp postcar_entry_failure |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 116 | |
| 117 | chipset_teardown_car: |
| 118 | |
| 119 | /* |
| 120 | * Retrieve return address from stack as it will get trashed below if |
| 121 | * execution is utilizing the cache-as-ram stack. |
| 122 | */ |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 123 | pop %esp |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 124 | |
| 125 | #else |
| 126 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 127 | movl %eax, %esp |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 128 | |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 129 | /* Register %esp is new stacktop for remaining of romstage. */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 130 | |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 131 | #endif |
| 132 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 133 | /* Disable cache */ |
| 134 | movl %cr0, %eax |
| 135 | orl $CR0_CacheDisable, %eax |
| 136 | movl %eax, %cr0 |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 137 | |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 138 | /* Register %esp is preserved in AMD_DISABLE_STACK. */ |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 139 | AMD_DISABLE_STACK |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 140 | |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 141 | #if IS_ENABLED(CONFIG_POSTCAR_STAGE) |
| 142 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 143 | jmp *%esp |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 144 | |
| 145 | #else |
| 146 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 147 | /* enable cache */ |
| 148 | movl %cr0, %eax |
| 149 | andl $0x9fffffff, %eax |
| 150 | movl %eax, %cr0 |
Siyuan Wang | f3b86b3 | 2012-11-01 18:51:15 +0800 | [diff] [blame] | 151 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 152 | call romstage_after_car |
Kyösti Mälkki | ba22e15 | 2016-11-23 06:47:15 +0200 | [diff] [blame] | 153 | |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 154 | #endif |
| 155 | |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 156 | /* Should never see this postcode */ |
| 157 | post_code(0xaf) |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 158 | |
Kyösti Mälkki | ba22e15 | 2016-11-23 06:47:15 +0200 | [diff] [blame] | 159 | stop: |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 160 | hlt |
| 161 | jmp stop |
Kyösti Mälkki | 63fac81 | 2017-09-02 16:41:43 +0300 | [diff] [blame] | 162 | |
| 163 | /* These are here for linking purposes. */ |
| 164 | .weak early_all_cores, romstage_main |
| 165 | early_all_cores: |
| 166 | romstage_main: |
| 167 | postcar_entry_failure: |
Elyes HAOUAS | dea45c1 | 2018-12-27 09:14:07 +0100 | [diff] [blame^] | 168 | /* Should never see this postcode */ |
| 169 | post_code(0xae) |
| 170 | jmp stop |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 171 | |
Kyösti Mälkki | 7076aa5 | 2017-09-02 16:20:15 +0300 | [diff] [blame] | 172 | _cache_as_ram_setup_end: |