Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | config SOC_AMD_CEZANNE |
| 4 | bool |
| 5 | help |
| 6 | AMD Cezanne support |
| 7 | |
| 8 | if SOC_AMD_CEZANNE |
| 9 | |
| 10 | config SOC_SPECIFIC_OPTIONS |
| 11 | def_bool y |
Raul E Rangel | 24d024a | 2021-02-12 16:07:43 -0700 | [diff] [blame] | 12 | select ACPI_SOC_NVS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 13 | select ARCH_BOOTBLOCK_X86_32 |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 14 | select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 15 | select ARCH_ROMSTAGE_X86_32 |
| 16 | select ARCH_RAMSTAGE_X86_32 |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 17 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Mathew King | c519bff | 2021-03-04 08:26:51 -0700 | [diff] [blame] | 18 | select DRIVERS_USB_ACPI |
Zheng Bao | 7b13e4e | 2021-03-16 16:13:56 +0800 | [diff] [blame] | 19 | select DRIVERS_I2C_DESIGNWARE |
Mathew King | c519bff | 2021-03-04 08:26:51 -0700 | [diff] [blame] | 20 | select DRIVERS_USB_PCI_XHCI |
Felix Held | c963499 | 2021-01-26 21:35:39 +0100 | [diff] [blame] | 21 | select FSP_COMPRESS_FSP_M_LZMA |
| 22 | select FSP_COMPRESS_FSP_S_LZMA |
Raul E Rangel | e925af2 | 2021-03-30 16:32:20 -0600 | [diff] [blame] | 23 | select GENERIC_GPIO_LIB |
Felix Held | 8602495 | 2021-02-03 23:44:28 +0100 | [diff] [blame] | 24 | select HAVE_ACPI_TABLES |
Felix Held | 44f4153 | 2020-12-09 02:01:16 +0100 | [diff] [blame] | 25 | select HAVE_CF9_RESET |
Felix Held | 227c649 | 2021-03-22 14:44:58 +0100 | [diff] [blame] | 26 | select HAVE_EM100_SUPPORT |
Nikolai Vyssotski | 0671d73 | 2021-03-11 19:12:38 -0600 | [diff] [blame] | 27 | select HAVE_FSP_GOP |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 28 | select HAVE_SMI_HANDLER |
Felix Held | cb97734 | 2021-01-19 20:36:38 +0100 | [diff] [blame] | 29 | select IDT_IN_EVERY_STAGE |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 30 | select IOAPIC |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 31 | select PARALLEL_MP |
| 32 | select PARALLEL_MP_AP_WORK |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 33 | select PLATFORM_USES_FSP2_0 |
Raul E Rangel | 95b3dc3 | 2021-03-24 16:53:37 -0600 | [diff] [blame] | 34 | select PROVIDES_ROM_SHARING |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 35 | select RESET_VECTOR_IN_RAM |
Felix Held | 7cd81b9 | 2021-02-11 14:58:08 +0100 | [diff] [blame] | 36 | select RTC |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 37 | select SOC_AMD_COMMON |
Karthikeyan Ramasubramanian | fbb027e | 2021-04-23 11:48:06 -0600 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_ACP |
Felix Held | bb4bee85 | 2021-02-10 16:53:53 +0100 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 64de2c1 | 2020-12-05 20:53:59 +0100 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Eric Lai | 65b0afe | 2021-04-09 11:50:48 +0800 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
Felix Held | 62ef88f | 2020-12-08 23:18:19 +0100 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_AOAC |
Felix Held | 9a6bc07 | 2021-03-05 00:14:08 +0100 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_APOB |
Felix Held | 07462ef | 2020-12-11 15:55:45 +0100 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | ea32c52 | 2021-02-13 01:42:44 +0100 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Nikolai Vyssotski | 0671d73 | 2021-03-11 19:12:38 -0600 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Felix Held | 28e2353 | 2021-02-24 20:52:08 +0100 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Zheng Bao | b0f00ed | 2021-03-16 15:28:49 +0800 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_I2C |
Zheng Bao | 3da5569 | 2021-01-26 18:30:18 +0800 | [diff] [blame] | 49 | select SOC_AMD_COMMON_BLOCK_LPC |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_NONCAR |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 52 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Raul E Rangel | e4f8317 | 2021-05-10 14:49:55 -0600 | [diff] [blame] | 53 | select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
Karthikeyan Ramasubramanian | f62bbc8 | 2021-03-30 15:19:12 -0600 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_PM |
Martin Roth | 31f7a72 | 2021-03-23 14:53:58 -0600 | [diff] [blame] | 55 | select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
Felix Held | 338d670 | 2021-01-29 23:13:56 +0100 | [diff] [blame] | 56 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 57 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Zheng Bao | 02a5ddd | 2020-12-15 22:16:51 +0800 | [diff] [blame] | 58 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 59 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 7f3f52d | 2021-03-03 18:56:41 +0100 | [diff] [blame] | 60 | select SOC_AMD_COMMON_BLOCK_SMU |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 61 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 65783fb | 2020-12-04 17:38:46 +0100 | [diff] [blame] | 62 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 63 | select SOC_AMD_COMMON_BLOCK_UART |
Raul E Rangel | 35dc4b0 | 2021-02-12 16:04:27 -0700 | [diff] [blame] | 64 | select SOC_AMD_COMMON_BLOCK_UCODE |
Raul E Rangel | fd7ed87 | 2021-05-04 15:42:09 -0600 | [diff] [blame] | 65 | select SOC_AMD_COMMON_FSP_PCI |
Felix Held | cc975c5 | 2021-01-23 00:18:08 +0100 | [diff] [blame] | 66 | select SSE2 |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 67 | select UDK_2017_BINDING |
Felix Held | f09221c | 2021-01-22 23:50:54 +0100 | [diff] [blame] | 68 | select X86_AMD_FIXED_MTRRS |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 69 | select X86_AMD_INIT_SIPI |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 70 | |
Raul E Rangel | 35dc4b0 | 2021-02-12 16:04:27 -0700 | [diff] [blame] | 71 | config SOC_AMD_COMMON_BLOCK_UCODE_SIZE |
| 72 | default 5568 |
| 73 | |
Furquan Shaikh | 696f4ea | 2021-01-08 11:48:52 -0800 | [diff] [blame] | 74 | config CHIPSET_DEVICETREE |
| 75 | string |
| 76 | default "soc/amd/cezanne/chipset.cb" |
| 77 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 78 | config EARLY_RESERVED_DRAM_BASE |
| 79 | hex |
| 80 | default 0x2000000 |
| 81 | help |
| 82 | This variable defines the base address of the DRAM which is reserved |
| 83 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 84 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 85 | not use it, thus preventing corruption of OS memory in case of S3 |
| 86 | resume. |
| 87 | |
| 88 | config EARLYRAM_BSP_STACK_SIZE |
| 89 | hex |
| 90 | default 0x1000 |
| 91 | |
| 92 | config PSP_APOB_DRAM_ADDRESS |
| 93 | hex |
| 94 | default 0x2001000 |
| 95 | help |
| 96 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 97 | Block. |
| 98 | |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 99 | config PSP_SHAREDMEM_BASE |
| 100 | hex |
| 101 | default 0x2011000 if VBOOT |
| 102 | default 0x0 |
| 103 | help |
| 104 | This variable defines the base address in DRAM memory where PSP copies |
| 105 | the vboot workbuf. This is used in the linker script to have a static |
| 106 | allocation for the buffer as well as for adding relevant entries in |
| 107 | the BIOS directory table for the PSP. |
| 108 | |
| 109 | config PSP_SHAREDMEM_SIZE |
| 110 | hex |
| 111 | default 0x8000 if VBOOT |
| 112 | default 0x0 |
| 113 | help |
| 114 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 115 | any logs or timestamps back to coreboot. This will be copied |
| 116 | into main memory by the PSP and will be available when the x86 is |
| 117 | started. The workbuf's base depends on the address of the reset |
| 118 | vector. |
| 119 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 120 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 121 | hex |
| 122 | default 0x1600 |
| 123 | help |
| 124 | Increase this value if preram cbmem console is getting truncated |
| 125 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 126 | config C_ENV_BOOTBLOCK_SIZE |
| 127 | hex |
| 128 | default 0x10000 |
| 129 | help |
| 130 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 131 | This variable controls the DRAM allocation size in linker script |
| 132 | for bootblock stage. |
| 133 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 134 | config ROMSTAGE_ADDR |
| 135 | hex |
| 136 | default 0x2040000 |
| 137 | help |
| 138 | Sets the address in DRAM where romstage should be loaded. |
| 139 | |
| 140 | config ROMSTAGE_SIZE |
| 141 | hex |
| 142 | default 0x80000 |
| 143 | help |
| 144 | Sets the size of DRAM allocation for romstage in linker script. |
| 145 | |
| 146 | config FSP_M_ADDR |
| 147 | hex |
| 148 | default 0x20C0000 |
| 149 | help |
| 150 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 151 | performs relocation of FSP-M to this address. |
| 152 | |
| 153 | config FSP_M_SIZE |
| 154 | hex |
| 155 | default 0x80000 |
| 156 | help |
| 157 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 158 | |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 159 | config FSP_TEMP_RAM_SIZE |
| 160 | hex |
| 161 | default 0x40000 |
| 162 | help |
| 163 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 164 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 165 | config VERSTAGE_ADDR |
| 166 | hex |
| 167 | depends on VBOOT_SEPARATE_VERSTAGE |
| 168 | default 0x2140000 |
| 169 | help |
| 170 | Sets the address in DRAM where verstage should be loaded if running |
| 171 | as a separate stage on x86. |
| 172 | |
| 173 | config VERSTAGE_SIZE |
| 174 | hex |
| 175 | depends on VBOOT_SEPARATE_VERSTAGE |
| 176 | default 0x80000 |
| 177 | help |
| 178 | Sets the size of DRAM allocation for verstage in linker script if |
| 179 | running as a separate stage on x86. |
| 180 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 181 | config RAMBASE |
| 182 | hex |
| 183 | default 0x10000000 |
| 184 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 185 | config RO_REGION_ONLY |
| 186 | string |
| 187 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 188 | default "apu/amdfw" |
| 189 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 190 | config CPU_ADDR_BITS |
| 191 | int |
| 192 | default 48 |
| 193 | |
| 194 | config MMCONF_BASE_ADDRESS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 195 | default 0xF8000000 |
| 196 | |
| 197 | config MMCONF_BUS_NUMBER |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 198 | default 64 |
| 199 | |
Felix Held | 8861562 | 2021-01-19 23:51:45 +0100 | [diff] [blame] | 200 | config MAX_CPUS |
| 201 | int |
| 202 | default 16 |
Felix Held | b77387f | 2021-04-23 22:16:04 +0200 | [diff] [blame] | 203 | help |
| 204 | Maximum number of threads the platform can have. |
Felix Held | 8861562 | 2021-01-19 23:51:45 +0100 | [diff] [blame] | 205 | |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 206 | config CONSOLE_UART_BASE_ADDRESS |
| 207 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 208 | hex |
| 209 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 210 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 211 | |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 212 | config SMM_TSEG_SIZE |
| 213 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 214 | default 0x800000 if HAVE_SMI_HANDLER |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 215 | default 0x0 |
| 216 | |
| 217 | config SMM_RESERVED_SIZE |
| 218 | hex |
| 219 | default 0x180000 |
| 220 | |
| 221 | config SMM_MODULE_STACK_SIZE |
| 222 | hex |
| 223 | default 0x800 |
| 224 | |
Felix Held | 90b0701 | 2021-04-15 20:23:56 +0200 | [diff] [blame] | 225 | config ACPI_BERT |
| 226 | bool "Build ACPI BERT Table" |
| 227 | default y |
| 228 | depends on HAVE_ACPI_TABLES |
| 229 | help |
| 230 | Report Machine Check errors identified in POST to the OS in an |
| 231 | ACPI Boot Error Record Table. |
| 232 | |
| 233 | config ACPI_BERT_SIZE |
| 234 | hex |
| 235 | default 0x4000 if ACPI_BERT |
| 236 | default 0x0 |
| 237 | help |
| 238 | Specify the amount of DRAM reserved for gathering the data used to |
| 239 | generate the ACPI table. |
| 240 | |
Zheng Bao | 7b13e4e | 2021-03-16 16:13:56 +0800 | [diff] [blame] | 241 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 242 | int |
| 243 | default 150 |
| 244 | |
Raul E Rangel | 95b3dc3 | 2021-03-24 16:53:37 -0600 | [diff] [blame] | 245 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 246 | def_bool n |
| 247 | help |
| 248 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 249 | which indicates a board level ROM transaction request. This |
| 250 | removes arbitration with board and assumes the chipset controls |
| 251 | the SPI flash bus entirely. |
| 252 | |
Felix Held | 27b295b | 2021-03-25 01:20:41 +0100 | [diff] [blame] | 253 | config DISABLE_KEYBOARD_RESET_PIN |
| 254 | bool |
| 255 | help |
| 256 | Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| 257 | signal. When this pin is used as GPIO and the keyboard reset |
| 258 | functionality isn't disabled, configuring it as an output and driving |
| 259 | it as 0 will cause a reset. |
| 260 | |
Jason Glenesk | 79542fa | 2021-03-10 03:50:57 -0800 | [diff] [blame] | 261 | config ACPI_SSDT_PSD_INDEPENDENT |
| 262 | bool "Allow core p-state independent transitions" |
| 263 | default y |
| 264 | help |
| 265 | AMD recommends the ACPI _PSD object to be configured to cause |
| 266 | cores to transition between p-states independently. A vendor may |
| 267 | choose to generate _PSD object to allow cores to transition together. |
| 268 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 269 | menu "PSP Configuration Options" |
| 270 | |
| 271 | config AMD_FWM_POSITION_INDEX |
| 272 | int "Firmware Directory Table location (0 to 5)" |
| 273 | range 0 5 |
| 274 | default 0 if BOARD_ROMSIZE_KB_512 |
| 275 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 276 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 277 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 278 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 279 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 280 | help |
| 281 | Typically this is calculated by the ROM size, but there may |
| 282 | be situations where you want to put the firmware directory |
| 283 | table in a different location. |
| 284 | 0: 512 KB - 0xFFFA0000 |
| 285 | 1: 1 MB - 0xFFF20000 |
| 286 | 2: 2 MB - 0xFFE20000 |
| 287 | 3: 4 MB - 0xFFC20000 |
| 288 | 4: 8 MB - 0xFF820000 |
| 289 | 5: 16 MB - 0xFF020000 |
| 290 | |
| 291 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 292 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 293 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 294 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 295 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 296 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 297 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 298 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 299 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 300 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 301 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 302 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 303 | |
| 304 | config AMDFW_CONFIG_FILE |
| 305 | string |
| 306 | default "src/soc/amd/cezanne/fw.cfg" |
| 307 | |
Rob Barnes | e09b681 | 2021-04-15 17:21:19 -0600 | [diff] [blame] | 308 | config PSP_DISABLE_POSTCODES |
| 309 | bool "Disable PSP post codes" |
| 310 | help |
| 311 | Disables the output of port80 post codes from PSP. |
| 312 | |
| 313 | config PSP_POSTCODES_ON_ESPI |
| 314 | bool "Use eSPI bus for PSP post codes" |
| 315 | default y |
| 316 | depends on !PSP_DISABLE_POSTCODES |
| 317 | help |
| 318 | Select to send PSP port80 post codes on eSPI bus. |
| 319 | If not selected, PSP port80 codes will be sent on LPC bus. |
| 320 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 321 | config PSP_LOAD_MP2_FW |
| 322 | bool |
| 323 | default n |
| 324 | help |
| 325 | Include the MP2 firmwares and configuration into the PSP build. |
| 326 | |
| 327 | If unsure, answer 'n' |
| 328 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 329 | config PSP_UNLOCK_SECURE_DEBUG |
| 330 | bool "Unlock secure debug" |
| 331 | default y |
| 332 | help |
| 333 | Select this item to enable secure debug options in PSP. |
| 334 | |
Raul E Rangel | 97b8b17 | 2021-02-24 16:59:32 -0700 | [diff] [blame] | 335 | config HAVE_PSP_WHITELIST_FILE |
| 336 | bool "Include a debug whitelist file in PSP build" |
| 337 | default n |
| 338 | help |
| 339 | Support secured unlock prior to reset using a whitelisted |
| 340 | serial number. This feature requires a signed whitelist image |
| 341 | and bootloader from AMD. |
| 342 | |
| 343 | If unsure, answer 'n' |
| 344 | |
| 345 | config PSP_WHITELIST_FILE |
| 346 | string "Debug whitelist file path" |
| 347 | depends on HAVE_PSP_WHITELIST_FILE |
| 348 | default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" |
| 349 | |
Martin Roth | fdad5ad | 2021-04-16 11:36:01 -0600 | [diff] [blame] | 350 | config PSP_SOFTFUSE_BITS |
| 351 | string "PSP Soft Fuse bits to enable" |
| 352 | default "28 6" |
| 353 | help |
| 354 | Space separated list of Soft Fuse bits to enable. |
| 355 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 356 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 357 | (Set by PSP_DISABLE_PORT80) |
| 358 | Bit 15: PSP post code destination: 0=LPC 1=eSPI |
| 359 | (Set by PSP_INITIALIZE_ESPI) |
| 360 | Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| 361 | |
| 362 | See #55758 (NDA) for additional bit definitions. |
| 363 | |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 364 | config PSP_VERSTAGE_FILE |
| 365 | string "Specify the PSP_verstage file path" |
| 366 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 367 | default "$(obj)/psp_verstage.bin" |
| 368 | help |
| 369 | Add psp_verstage file to the build & PSP Directory Table |
| 370 | |
| 371 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 372 | string "Specify the PSP_verstage Signature Token file path" |
| 373 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 374 | default "" |
| 375 | help |
| 376 | Add psp_verstage signature token to the build & PSP Directory Table |
| 377 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 378 | endmenu |
| 379 | |
Raul E Rangel | 06d1e4d | 2021-04-09 14:42:06 -0600 | [diff] [blame] | 380 | config VBOOT |
| 381 | select VBOOT_VBNV_CMOS |
| 382 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 383 | |
Kangheui Won | 66c5f25 | 2021-04-20 17:30:29 +1000 | [diff] [blame] | 384 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 385 | def_bool n |
| 386 | depends on VBOOT |
| 387 | select ARCH_VERSTAGE_ARMV7 |
| 388 | help |
| 389 | Runs verstage on the PSP. Only available on |
| 390 | certain Chrome OS branded parts from AMD. |
| 391 | |
| 392 | config VBOOT_HASH_BLOCK_SIZE |
| 393 | hex |
| 394 | default 0x9000 |
| 395 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 396 | help |
| 397 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 398 | spent in the overhead of doing svc calls, increasing the hash block |
| 399 | size significantly cuts the verstage hashing time as seen below. |
| 400 | |
| 401 | 4k takes 180ms |
| 402 | 16k takes 44ms |
| 403 | 32k takes 33.7ms |
| 404 | 36k takes 32.5ms |
| 405 | There's actually still room for an even bigger stack, but we've |
| 406 | reached a point of diminishing returns. |
| 407 | |
| 408 | config CMOS_RECOVERY_BYTE |
| 409 | hex |
| 410 | default 0x51 |
| 411 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 412 | help |
| 413 | If the workbuf is not passed from the PSP to coreboot, set the |
| 414 | recovery flag and reboot. The PSP will read this byte, mark the |
| 415 | recovery request in VBNV, and reset the system into recovery mode. |
| 416 | |
| 417 | This is the byte before the default first byte used by VBNV |
| 418 | (0x26 + 0x0E - 1) |
| 419 | |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 420 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 421 | |
| 422 | config RWA_REGION_ONLY |
| 423 | string |
| 424 | default "apu/amdfw_a" |
| 425 | help |
| 426 | Add a space-delimited list of filenames that should only be in the |
| 427 | RW-A section. |
| 428 | |
| 429 | config RWB_REGION_ONLY |
| 430 | string |
| 431 | default "apu/amdfw_b" |
| 432 | help |
| 433 | Add a space-delimited list of filenames that should only be in the |
| 434 | RW-B section. |
| 435 | |
| 436 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 437 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 438 | endif # SOC_AMD_CEZANNE |