Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Felix Singer | cc93db9 | 2023-10-23 16:26:20 +0200 | [diff] [blame] | 3 | register "SataPortsEnable" = "{ |
| 4 | [0] = 1, |
| 5 | [1] = 1, |
| 6 | [2] = 1, |
| 7 | }" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 8 | |
| 9 | # Enable deep Sx states |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 10 | register "deep_s5_enable_ac" = "1" |
| 11 | register "deep_s5_enable_dc" = "1" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 12 | |
| 13 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 14 | register "gen2_dec" = "0x000c0201" |
| 15 | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 16 | # VR Settings Configuration for 4 Domains |
| 17 | #+----------------+-------+-------+-------+-------+ |
| 18 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 19 | #+----------------+-------+-------+-------+-------+ |
| 20 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 21 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 22 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 23 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 24 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 25 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 26 | #| ImonOffset | 0 | 0 | 0 | 0 | |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 27 | #| IccMax | Auto | Auto | Auto | Auto | |
| 28 | #| VrVoltageLimit*| 0 | 0 | 0 | 0 | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 29 | #+----------------+-------+-------+-------+-------+ |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 30 | #* VrVoltageLimit command not sent. |
| 31 | |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 32 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 33 | .vr_config_enable = 1, |
| 34 | .psi1threshold = VR_CFG_AMP(20), |
| 35 | .psi2threshold = VR_CFG_AMP(5), |
| 36 | .psi3threshold = VR_CFG_AMP(1), |
| 37 | .psi3enable = 1, |
| 38 | .psi4enable = 1, |
| 39 | .imon_slope = 0, |
| 40 | .imon_offset = 0, |
| 41 | .icc_max = 0, |
| 42 | .voltage_limit = 0 |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 43 | }" |
| 44 | |
| 45 | register "domain_vr_config[VR_IA_CORE]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 46 | .vr_config_enable = 1, |
| 47 | .psi1threshold = VR_CFG_AMP(20), |
| 48 | .psi2threshold = VR_CFG_AMP(5), |
| 49 | .psi3threshold = VR_CFG_AMP(1), |
| 50 | .psi3enable = 1, |
| 51 | .psi4enable = 1, |
| 52 | .imon_slope = 0, |
| 53 | .imon_offset = 0, |
| 54 | .icc_max = 0, |
| 55 | .voltage_limit = 0 |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 56 | }" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 57 | |
| 58 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 59 | .vr_config_enable = 1, |
| 60 | .psi1threshold = VR_CFG_AMP(20), |
| 61 | .psi2threshold = VR_CFG_AMP(5), |
| 62 | .psi3threshold = VR_CFG_AMP(1), |
| 63 | .psi3enable = 1, |
| 64 | .psi4enable = 1, |
| 65 | .imon_slope = 0, |
| 66 | .imon_offset = 0, |
| 67 | .icc_max = 0, |
| 68 | .voltage_limit = 0 |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 69 | }" |
| 70 | |
| 71 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 72 | .vr_config_enable = 1, |
| 73 | .psi1threshold = VR_CFG_AMP(20), |
| 74 | .psi2threshold = VR_CFG_AMP(5), |
| 75 | .psi3threshold = VR_CFG_AMP(1), |
| 76 | .psi3enable = 1, |
| 77 | .psi4enable = 1, |
| 78 | .imon_slope = 0, |
| 79 | .imon_offset = 0, |
| 80 | .icc_max = 0, |
| 81 | .voltage_limit = 0 |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 82 | }" |
| 83 | |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 84 | # Enable Root ports. |
| 85 | register "PcieRpEnable[2]" = "1" |
| 86 | register "PcieRpEnable[3]" = "1" |
| 87 | register "PcieRpEnable[4]" = "1" |
| 88 | register "PcieRpEnable[5]" = "1" |
| 89 | register "PcieRpEnable[8]" = "1" |
| 90 | |
| 91 | # Enable CLKREQ# |
| 92 | register "PcieRpClkReqSupport[2]" = "1" |
| 93 | register "PcieRpClkReqSupport[3]" = "1" |
| 94 | register "PcieRpClkReqSupport[4]" = "1" |
| 95 | register "PcieRpClkReqSupport[5]" = "1" |
| 96 | register "PcieRpClkReqSupport[8]" = "1" |
| 97 | |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 98 | # RP 3 uses SRCCLKREQ5# |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 99 | register "PcieRpClkReqNumber[2]" = "5" |
| 100 | register "PcieRpClkReqNumber[3]" = "2" |
| 101 | register "PcieRpClkReqNumber[4]" = "3" |
| 102 | register "PcieRpClkReqNumber[5]" = "4" |
| 103 | register "PcieRpClkReqNumber[8]" = "1" |
| 104 | |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 105 | # RP 3 uses CLK SRC 5# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 106 | register "PcieRpClkSrcNumber[2]" = "5" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 107 | # RP 4 uses CLK SRC 2# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 108 | register "PcieRpClkSrcNumber[3]" = "2" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 109 | # RP 5 uses CLK SRC 3# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 110 | register "PcieRpClkSrcNumber[4]" = "3" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 111 | # RP 6 uses CLK SRC 4# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 112 | register "PcieRpClkSrcNumber[5]" = "4" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 113 | # RP 9 uses CLK SRC 1# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 114 | register "PcieRpClkSrcNumber[8]" = "1" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 115 | |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 116 | |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 117 | register "SerialIoDevMode" = "{ |
| 118 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 119 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 120 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 121 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 122 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 123 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 124 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 125 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 126 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 127 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 128 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 129 | }" |
| 130 | |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 131 | # Use default SD card detect GPIO configuration |
Angel Pons | 6bd99f9 | 2021-02-20 00:16:47 +0100 | [diff] [blame] | 132 | register "sdcard_cd_gpio" = "GPP_G5" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 133 | |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 134 | device domain 0 on |
Felix Singer | 6c83a71 | 2024-06-23 00:25:18 +0200 | [diff] [blame^] | 135 | device ref south_xhci on |
| 136 | register "usb2_ports" = "{ |
| 137 | [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ |
| 138 | [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ |
| 139 | [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ |
| 140 | [4] = USB2_PORT_MAX(OC1), /* Type-A Port */ |
| 141 | [5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 142 | [6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ |
| 143 | [7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ |
| 144 | [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 145 | [9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 146 | [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 147 | [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ |
| 148 | }" |
| 149 | |
| 150 | register "usb3_ports" = "{ |
| 151 | [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ |
| 152 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ |
| 153 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ |
| 154 | [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ |
| 155 | [4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */ |
| 156 | [5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ |
| 157 | }" |
| 158 | end |
Felix Singer | 2dff4f0 | 2023-11-16 01:17:31 +0100 | [diff] [blame] | 159 | device ref i2c2 off end |
| 160 | device ref i2c3 off end |
| 161 | device ref sata on end |
| 162 | device ref pcie_rp3 on end |
| 163 | device ref pcie_rp4 on end |
| 164 | device ref pcie_rp5 on end |
| 165 | device ref pcie_rp6 on end |
| 166 | device ref lpc_espi on |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 167 | chip drivers/pc80/tpm |
| 168 | device pnp 0c31.0 on end |
| 169 | end |
Felix Singer | 2dff4f0 | 2023-11-16 01:17:31 +0100 | [diff] [blame] | 170 | end |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 171 | end |
| 172 | end |