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Barnali Sarkar2ed14f62016-11-29 16:51:08 +05301chip soc/intel/skylake
2
3 # SATA port 0
Barnali Sarkar2ed14f62016-11-29 16:51:08 +05304 register "SataPortsEnable[0]" = "1"
5 register "SataPortsEnable[1]" = "1"
6 register "SataPortsEnable[2]" = "1"
7
8 # Enable deep Sx states
Duncan Laurie1fe32d62017-04-10 21:02:13 -07009 register "deep_s5_enable_ac" = "1"
10 register "deep_s5_enable_dc" = "1"
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053011
12 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053013 register "gen2_dec" = "0x000c0201"
14
Duncan Laurie4fa8a6f2017-03-14 16:37:55 -070015 # VR Settings Configuration for 4 Domains
16 #+----------------+-------+-------+-------+-------+
17 #| Domain/Setting | SA | IA | GTUS | GTS |
18 #+----------------+-------+-------+-------+-------+
19 #| Psi1Threshold | 20A | 20A | 20A | 20A |
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010020 #| Psi2Threshold | 5A | 5A | 5A | 5A |
Duncan Laurie4fa8a6f2017-03-14 16:37:55 -070021 #| Psi3Threshold | 1A | 1A | 1A | 1A |
22 #| Psi3Enable | 1 | 1 | 1 | 1 |
23 #| Psi4Enable | 1 | 1 | 1 | 1 |
24 #| ImonSlope | 0 | 0 | 0 | 0 |
25 #| ImonOffset | 0 | 0 | 0 | 0 |
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010026 #| IccMax | Auto | Auto | Auto | Auto |
27 #| VrVoltageLimit*| 0 | 0 | 0 | 0 |
Duncan Laurie4fa8a6f2017-03-14 16:37:55 -070028 #+----------------+-------+-------+-------+-------+
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010029 #* VrVoltageLimit command not sent.
30
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053031 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
32 .vr_config_enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010033 .psi1threshold = VR_CFG_AMP(20), \
34 .psi2threshold = VR_CFG_AMP(5), \
35 .psi3threshold = VR_CFG_AMP(1), \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053036 .psi3enable = 1, \
37 .psi4enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010038 .imon_slope = 0, \
39 .imon_offset = 0, \
40 .icc_max = 0, \
41 .voltage_limit = 0 \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053042 }"
43
44 register "domain_vr_config[VR_IA_CORE]" = "{
45 .vr_config_enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010046 .psi1threshold = VR_CFG_AMP(20), \
47 .psi2threshold = VR_CFG_AMP(5), \
48 .psi3threshold = VR_CFG_AMP(1), \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053049 .psi3enable = 1, \
50 .psi4enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010051 .imon_slope = 0, \
52 .imon_offset = 0, \
53 .icc_max = 0, \
54 .voltage_limit = 0 \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053055 }"
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053056
57 register "domain_vr_config[VR_GT_UNSLICED]" = "{
58 .vr_config_enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010059 .psi1threshold = VR_CFG_AMP(20), \
60 .psi2threshold = VR_CFG_AMP(5), \
61 .psi3threshold = VR_CFG_AMP(1), \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053062 .psi3enable = 1, \
63 .psi4enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010064 .imon_slope = 0, \
65 .imon_offset = 0, \
66 .icc_max = 0 ,\
67 .voltage_limit = 0 \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053068 }"
69
70 register "domain_vr_config[VR_GT_SLICED]" = "{
71 .vr_config_enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010072 .psi1threshold = VR_CFG_AMP(20), \
73 .psi2threshold = VR_CFG_AMP(5), \
74 .psi3threshold = VR_CFG_AMP(1), \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053075 .psi3enable = 1, \
76 .psi4enable = 1, \
Wim Vervoorn57aa8e32019-12-06 11:30:33 +010077 .imon_slope = 0, \
78 .imon_offset = 0, \
79 .icc_max = 0, \
80 .voltage_limit = 0 \
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053081 }"
82
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053083 # Enable Root ports.
84 register "PcieRpEnable[2]" = "1"
85 register "PcieRpEnable[3]" = "1"
86 register "PcieRpEnable[4]" = "1"
87 register "PcieRpEnable[5]" = "1"
88 register "PcieRpEnable[8]" = "1"
89
90 # Enable CLKREQ#
91 register "PcieRpClkReqSupport[2]" = "1"
92 register "PcieRpClkReqSupport[3]" = "1"
93 register "PcieRpClkReqSupport[4]" = "1"
94 register "PcieRpClkReqSupport[5]" = "1"
95 register "PcieRpClkReqSupport[8]" = "1"
96
Divya Chellape7fb7ce2017-12-19 20:16:50 +053097 # RP 3 uses SRCCLKREQ5#
Barnali Sarkar2ed14f62016-11-29 16:51:08 +053098 register "PcieRpClkReqNumber[2]" = "5"
99 register "PcieRpClkReqNumber[3]" = "2"
100 register "PcieRpClkReqNumber[4]" = "3"
101 register "PcieRpClkReqNumber[5]" = "4"
102 register "PcieRpClkReqNumber[8]" = "1"
103
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530104 # RP 3 uses uses CLK SRC 5#
105 register "PcieRpClkSrcNumber[2]" = "5"
106 # RP 4 uses uses CLK SRC 2#
107 register "PcieRpClkSrcNumber[3]" = "2"
108 # RP 5 uses uses CLK SRC 3#
109 register "PcieRpClkSrcNumber[4]" = "3"
110 # RP 6 uses uses CLK SRC 4#
111 register "PcieRpClkSrcNumber[5]" = "4"
112 # RP 9 uses uses CLK SRC 1#
113 register "PcieRpClkSrcNumber[8]" = "1"
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530114
115 # USB 2.0 Enable all ports
Angel Ponse16692e2020-08-03 12:54:48 +0200116 register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
117 register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
118 register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
119 register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port
120 register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
121 register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
122 register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
123 register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
124 register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
125 register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
126 register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530127
Angel Ponse16692e2020-08-03 12:54:48 +0200128 # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
129 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
130 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
131 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
132 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
133 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port
134 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530135
136 register "SerialIoDevMode" = "{ \
137 [PchSerialIoIndexI2C0] = PchSerialIoPci, \
138 [PchSerialIoIndexI2C1] = PchSerialIoPci, \
139 [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
140 [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
141 [PchSerialIoIndexI2C4] = PchSerialIoPci, \
142 [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
143 [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
144 [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
145 [PchSerialIoIndexUart0] = PchSerialIoPci, \
146 [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
147 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
148 }"
149
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530150
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530151
152 # Use default SD card detect GPIO configuration
Angel Pons6bd99f92021-02-20 00:16:47 +0100153 register "sdcard_cd_gpio" = "GPP_G5"
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530154
Subrata Banikc204aaa2017-08-17 15:49:58 +0530155 # Lock Down
Subrata Banikc4986eb2018-05-09 14:55:09 +0530156 register "common_soc_config" = "{
157 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
158 }"
Subrata Banikc204aaa2017-08-17 15:49:58 +0530159
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530160 device cpu_cluster 0 on
161 device lapic 0 on end
162 end
163 device domain 0 on
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530164 device pci 15.2 off end # I2C #2
165 device pci 15.3 off end # I2C #3
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530166 device pci 17.0 on end # SATA
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530167 device pci 19.1 off end # I2C #5
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530168 device pci 1c.2 on end # PCI Express Port 3
169 device pci 1c.3 on end # PCI Express Port 4
170 device pci 1c.4 on end # PCI Express Port 5
171 device pci 1c.5 on end # PCI Express Port 6
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530172 device pci 1f.0 on
173 chip drivers/pc80/tpm
174 device pnp 0c31.0 on end
175 end
176 end # LPC Interface
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530177 end
178end