Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # SATA port 0 |
| 4 | register "EnableSata" = "1" |
| 5 | register "SataPortsEnable[0]" = "1" |
| 6 | register "SataPortsEnable[1]" = "1" |
| 7 | register "SataPortsEnable[2]" = "1" |
| 8 | |
| 9 | # Enable deep Sx states |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 10 | register "deep_s5_enable_ac" = "1" |
| 11 | register "deep_s5_enable_dc" = "1" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 12 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 13 | |
| 14 | # GPE configuration |
| 15 | # Note that GPE events called out in ASL code rely on this |
| 16 | # route. i.e. If this route changes then the affected GPE |
| 17 | # offset bits also need to be changed. |
| 18 | register "gpe0_dw0" = "GPP_B" |
| 19 | register "gpe0_dw1" = "GPP_D" |
| 20 | register "gpe0_dw2" = "GPP_E" |
| 21 | |
| 22 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 23 | register "gen1_dec" = "0x00fc0801" |
| 24 | register "gen2_dec" = "0x000c0201" |
| 25 | |
| 26 | # Enable "Intel Speed Shift Technology" |
| 27 | register "speed_shift_enable" = "1" |
| 28 | |
| 29 | # Enable DPTF |
| 30 | register "dptf_enable" = "1" |
| 31 | |
| 32 | # FSP Configuration |
| 33 | register "SmbusEnable" = "1" |
| 34 | register "ScsEmmcEnabled" = "1" |
| 35 | register "ScsEmmcHs400Enabled" = "1" |
| 36 | register "ScsSdCardEnabled" = "2" |
| 37 | register "InternalGfx" = "1" |
| 38 | register "SkipExtGfxScan" = "1" |
| 39 | register "Device4Enable" = "1" |
| 40 | register "HeciEnabled" = "0" |
| 41 | register "SaGv" = "3" |
| 42 | register "PmTimerDisabled" = "1" |
| 43 | |
| 44 | register "pirqa_routing" = "PCH_IRQ11" |
| 45 | register "pirqb_routing" = "PCH_IRQ10" |
| 46 | register "pirqc_routing" = "PCH_IRQ11" |
| 47 | register "pirqd_routing" = "PCH_IRQ11" |
| 48 | register "pirqe_routing" = "PCH_IRQ11" |
| 49 | register "pirqf_routing" = "PCH_IRQ11" |
| 50 | register "pirqg_routing" = "PCH_IRQ11" |
| 51 | register "pirqh_routing" = "PCH_IRQ11" |
| 52 | |
| 53 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 54 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 55 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 56 | |
| 57 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 58 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 59 | |
| 60 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 61 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 62 | |
| 63 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 64 | register "PmConfigSlpAMinAssert" = "0x03" |
| 65 | |
| 66 | # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled |
| 67 | register "SerialIrqConfigSirqEnable" = "0x01" |
| 68 | |
Duncan Laurie | 4fa8a6f | 2017-03-14 16:37:55 -0700 | [diff] [blame] | 69 | # VR Settings Configuration for 4 Domains |
| 70 | #+----------------+-------+-------+-------+-------+ |
| 71 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 72 | #+----------------+-------+-------+-------+-------+ |
| 73 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 74 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 75 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 76 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 77 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 78 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 79 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 80 | #| IccMax | 7A | 34A | 35A | 35A | |
| 81 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 82 | #+----------------+-------+-------+-------+-------+ |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 83 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 84 | .vr_config_enable = 1, \ |
| 85 | .psi1threshold = 0x50, \ |
| 86 | .psi2threshold = 0x14, \ |
| 87 | .psi3threshold = 0x4, \ |
| 88 | .psi3enable = 1, \ |
| 89 | .psi4enable = 1, \ |
| 90 | .imon_slope = 0x0, \ |
| 91 | .imon_offset = 0x0, \ |
| 92 | .icc_max = 0x0, \ |
| 93 | .voltage_limit = 0x0 \ |
| 94 | }" |
| 95 | |
| 96 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 97 | .vr_config_enable = 1, \ |
| 98 | .psi1threshold = 0x50, \ |
| 99 | .psi2threshold = 0x14, \ |
| 100 | .psi3threshold = 0x4, \ |
| 101 | .psi3enable = 1, \ |
| 102 | .psi4enable = 1, \ |
| 103 | .imon_slope = 0x0, \ |
| 104 | .imon_offset = 0x0, \ |
| 105 | .icc_max = 0x0, \ |
| 106 | .voltage_limit = 0x0 \ |
| 107 | }" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 108 | |
| 109 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 110 | .vr_config_enable = 1, \ |
| 111 | .psi1threshold = 0x50, \ |
| 112 | .psi2threshold = 0x14, \ |
| 113 | .psi3threshold = 0x4, \ |
| 114 | .psi3enable = 1, \ |
| 115 | .psi4enable = 1, \ |
| 116 | .imon_slope = 0x0, \ |
| 117 | .imon_offset = 0x0, \ |
| 118 | .icc_max = 0x0 ,\ |
| 119 | .voltage_limit = 0x0 \ |
| 120 | }" |
| 121 | |
| 122 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 123 | .vr_config_enable = 1, \ |
| 124 | .psi1threshold = 0x50, \ |
| 125 | .psi2threshold = 0x14, \ |
| 126 | .psi3threshold = 0x4, \ |
| 127 | .psi3enable = 1, \ |
| 128 | .psi4enable = 1, \ |
| 129 | .imon_slope = 0x0, \ |
| 130 | .imon_offset = 0x0, \ |
| 131 | .icc_max = 0x0, \ |
| 132 | .voltage_limit = 0x0 \ |
| 133 | }" |
| 134 | |
| 135 | register "FspSkipMpInit" = "1" |
| 136 | |
| 137 | # Enable Root ports. |
| 138 | register "PcieRpEnable[2]" = "1" |
| 139 | register "PcieRpEnable[3]" = "1" |
| 140 | register "PcieRpEnable[4]" = "1" |
| 141 | register "PcieRpEnable[5]" = "1" |
| 142 | register "PcieRpEnable[8]" = "1" |
| 143 | |
| 144 | # Enable CLKREQ# |
| 145 | register "PcieRpClkReqSupport[2]" = "1" |
| 146 | register "PcieRpClkReqSupport[3]" = "1" |
| 147 | register "PcieRpClkReqSupport[4]" = "1" |
| 148 | register "PcieRpClkReqSupport[5]" = "1" |
| 149 | register "PcieRpClkReqSupport[8]" = "1" |
| 150 | |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame^] | 151 | # RP 3 uses SRCCLKREQ5# |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 152 | register "PcieRpClkReqNumber[2]" = "5" |
| 153 | register "PcieRpClkReqNumber[3]" = "2" |
| 154 | register "PcieRpClkReqNumber[4]" = "3" |
| 155 | register "PcieRpClkReqNumber[5]" = "4" |
| 156 | register "PcieRpClkReqNumber[8]" = "1" |
| 157 | |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame^] | 158 | # RP 3 uses uses CLK SRC 5# |
| 159 | register "PcieRpClkSrcNumber[2]" = "5" |
| 160 | # RP 4 uses uses CLK SRC 2# |
| 161 | register "PcieRpClkSrcNumber[3]" = "2" |
| 162 | # RP 5 uses uses CLK SRC 3# |
| 163 | register "PcieRpClkSrcNumber[4]" = "3" |
| 164 | # RP 6 uses uses CLK SRC 4# |
| 165 | register "PcieRpClkSrcNumber[5]" = "4" |
| 166 | # RP 9 uses uses CLK SRC 1# |
| 167 | register "PcieRpClkSrcNumber[8]" = "1" |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 168 | |
| 169 | # USB 2.0 Enable all ports |
| 170 | register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port |
| 171 | register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port |
| 172 | register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth |
| 173 | register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port |
| 174 | register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 175 | register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port |
| 176 | register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port |
| 177 | register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 178 | register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 179 | register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 180 | register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port |
| 181 | |
| 182 | # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled |
| 183 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port |
| 184 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 185 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 186 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port |
| 187 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port |
| 188 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port |
| 189 | |
| 190 | register "SerialIoDevMode" = "{ \ |
| 191 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 192 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 193 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 194 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 195 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 196 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 197 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 198 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 199 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 200 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 201 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ |
| 202 | }" |
| 203 | |
| 204 | # Send an extra VR mailbox command for the PS4 exit issue |
| 205 | register "SendVrMbxCmd" = "2" |
| 206 | |
| 207 | # Enable/Disable VMX feature |
| 208 | register "VmxEnable" = "0" |
| 209 | |
| 210 | # Use default SD card detect GPIO configuration |
| 211 | register "sdcard_cd_gpio_default" = "GPP_G5" |
| 212 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 213 | # Lock Down |
| 214 | register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" |
| 215 | |
Barnali Sarkar | 2ed14f6 | 2016-11-29 16:51:08 +0530 | [diff] [blame] | 216 | device cpu_cluster 0 on |
| 217 | device lapic 0 on end |
| 218 | end |
| 219 | device domain 0 on |
| 220 | device pci 00.0 on end # Host Bridge |
| 221 | device pci 02.0 on end # Integrated Graphics Device |
| 222 | device pci 14.0 on end # USB xHCI |
| 223 | device pci 14.1 off end # USB xDCI (OTG) |
| 224 | device pci 14.2 on end # Thermal Subsystem |
| 225 | device pci 15.0 on end # I2C #0 |
| 226 | device pci 15.1 on end # I2C #1 |
| 227 | device pci 15.2 off end # I2C #2 |
| 228 | device pci 15.3 off end # I2C #3 |
| 229 | device pci 16.0 on end # Management Engine Interface 1 |
| 230 | device pci 16.1 off end # Management Engine Interface 2 |
| 231 | device pci 16.2 off end # Management Engine IDE-R |
| 232 | device pci 16.3 off end # Management Engine KT Redirection |
| 233 | device pci 16.4 off end # Management Engine Interface 3 |
| 234 | device pci 17.0 on end # SATA |
| 235 | device pci 19.0 on end # UART #2 |
| 236 | device pci 19.1 off end # I2C #5 |
| 237 | device pci 19.2 on end # |
| 238 | device pci 1c.0 on end # PCI Express Port 1 |
| 239 | device pci 1c.1 off end # PCI Express Port 2 |
| 240 | device pci 1c.2 on end # PCI Express Port 3 |
| 241 | device pci 1c.3 on end # PCI Express Port 4 |
| 242 | device pci 1c.4 on end # PCI Express Port 5 |
| 243 | device pci 1c.5 on end # PCI Express Port 6 |
| 244 | device pci 1c.6 off end # PCI Express Port 7 |
| 245 | device pci 1c.7 off end # PCI Express Port 8 |
| 246 | device pci 1d.0 on end # PCI Express Port 9 |
| 247 | device pci 1d.1 off end # PCI Express Port 10 |
| 248 | device pci 1d.2 off end # PCI Express Port 11 |
| 249 | device pci 1d.3 off end # PCI Express Port 12 |
| 250 | device pci 1e.0 on end # UART #0 |
| 251 | device pci 1e.1 off end # UART #1 |
| 252 | device pci 1e.2 off end # GSPI #0 |
| 253 | device pci 1e.3 off end # GSPI #1 |
| 254 | device pci 1e.4 on end # eMMC |
| 255 | device pci 1e.5 off end # SDIO |
| 256 | device pci 1e.6 on end # SDCard |
| 257 | device pci 1f.0 on |
| 258 | chip drivers/pc80/tpm |
| 259 | device pnp 0c31.0 on end |
| 260 | end |
| 261 | end # LPC Interface |
| 262 | device pci 1f.1 on end # P2SB |
| 263 | device pci 1f.2 on end # Power Management Controller |
| 264 | device pci 1f.3 on end # Intel HDA |
| 265 | device pci 1f.4 on end # SMBus |
| 266 | device pci 1f.5 on end # PCH SPI |
| 267 | device pci 1f.6 off end # GbE |
| 268 | end |
| 269 | end |