Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 2 | |
Eran Mitrani | 4c9440c | 2022-11-29 17:46:38 -0800 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 4 | #include <acpi/acpi_pm.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpigen.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 6 | #include <arch/ioapic.h> |
| 7 | #include <arch/smp/mpspec.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 8 | #include <console/console.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 9 | #include <cpu/cpu.h> |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 10 | #include <cpu/intel/common/common.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 11 | #include <cpu/intel/msr.h> |
| 12 | #include <cpu/intel/turbo.h> |
| 13 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | ca71e13 | 2021-01-15 05:06:35 +0200 | [diff] [blame] | 14 | #include <intelblocks/acpi_wake_source.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 15 | #include <intelblocks/acpi.h> |
Marc Jones | 1403b91 | 2020-12-02 14:35:27 -0700 | [diff] [blame] | 16 | #include <intelblocks/lpc_lib.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 17 | #include <intelblocks/pmclib.h> |
Michael Niewöhner | b48caad | 2021-10-17 15:36:45 +0200 | [diff] [blame] | 18 | #include <intelblocks/sgx.h> |
Marek Maslanka | 531c45e | 2024-01-12 07:24:21 +0000 | [diff] [blame] | 19 | #include <intelblocks/tco.h> |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 20 | #include <intelblocks/uart.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 21 | #include <soc/gpio.h> |
Marek Maslanka | 531c45e | 2024-01-12 07:24:21 +0000 | [diff] [blame] | 22 | #include <soc/intel/common/tco.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 23 | #include <soc/iomap.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 24 | #include <soc/pm.h> |
| 25 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 26 | #define CPUID_6_EAX_ISST (1 << 7) |
| 27 | |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 28 | #define ACPI_SCI_IRQ 9 |
| 29 | |
| 30 | void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 31 | { |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 32 | int sci_irq = ACPI_SCI_IRQ; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 33 | uint32_t scis; |
| 34 | |
| 35 | scis = soc_read_sci_irq_select(); |
| 36 | scis &= SCI_IRQ_SEL; |
| 37 | scis >>= SCI_IRQ_ADJUST; |
| 38 | |
| 39 | /* Determine how SCI is routed. */ |
| 40 | switch (scis) { |
| 41 | case SCIS_IRQ9: |
| 42 | case SCIS_IRQ10: |
| 43 | case SCIS_IRQ11: |
| 44 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 45 | break; |
| 46 | case SCIS_IRQ20: |
| 47 | case SCIS_IRQ21: |
| 48 | case SCIS_IRQ22: |
| 49 | case SCIS_IRQ23: |
| 50 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 51 | break; |
| 52 | default: |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 53 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 54 | break; |
| 55 | } |
| 56 | |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 57 | *gsi = sci_irq; |
| 58 | *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; |
| 59 | *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); |
| 60 | |
| 61 | printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 62 | } |
| 63 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 64 | |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 65 | static const uintptr_t default_ioapic_bases[] = { IO_APIC_ADDR }; |
| 66 | |
| 67 | __weak size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) |
Marc Jones | 847043c | 2020-12-02 11:24:00 -0700 | [diff] [blame] | 68 | { |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 69 | *ioapic_bases = default_ioapic_bases; |
| 70 | return ARRAY_SIZE(default_ioapic_bases); |
Marc Jones | 847043c | 2020-12-02 11:24:00 -0700 | [diff] [blame] | 71 | } |
| 72 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 73 | unsigned long acpi_fill_madt(unsigned long current) |
| 74 | { |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 75 | const uintptr_t *ioapic_table; |
Marc Jones | 847043c | 2020-12-02 11:24:00 -0700 | [diff] [blame] | 76 | size_t ioapic_entries; |
| 77 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 78 | /* Local APICs */ |
Kyösti Mälkki | 69a1396 | 2023-04-08 14:10:48 +0300 | [diff] [blame] | 79 | if (!CONFIG(ACPI_COMMON_MADT_LAPIC)) |
Sridhar Siricilla | 7301cfa | 2023-01-19 18:50:09 +0530 | [diff] [blame] | 80 | current = acpi_create_madt_lapics_with_nmis_hybrid(current); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 81 | |
| 82 | /* IOAPIC */ |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 83 | ioapic_entries = soc_get_ioapic_info(&ioapic_table); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 84 | |
Kyösti Mälkki | 8eac12f | 2023-04-12 14:04:44 +0300 | [diff] [blame] | 85 | /* Default SOC IOAPIC entry */ |
| 86 | ASSERT(ioapic_table[0] == IO_APIC_ADDR); |
| 87 | |
| 88 | for (int i = 1; i < ioapic_entries; i++) |
| 89 | current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); |
Kyösti Mälkki | ae1b2d4 | 2023-04-10 16:45:39 +0300 | [diff] [blame] | 90 | |
| 91 | return current; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 94 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 95 | { |
| 96 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 97 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 98 | |
| 99 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 100 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 101 | |
| 102 | fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| 103 | |
| 104 | fadt->pm1_evt_len = 4; |
| 105 | fadt->pm1_cnt_len = 2; |
| 106 | |
| 107 | /* GPE0 STS/EN pairs each 32 bits wide. */ |
| 108 | fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); |
| 109 | |
Kyösti Mälkki | 88decca | 2023-04-28 07:04:34 +0300 | [diff] [blame] | 110 | fill_fadt_extended_pm_io(fadt); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 111 | |
Angel Pons | a208c6c | 2020-07-13 00:02:34 +0200 | [diff] [blame] | 112 | fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
Michael Niewöhner | 2353cd9 | 2021-10-04 16:59:49 +0200 | [diff] [blame] | 113 | ACPI_FADT_SLEEP_BUTTON | |
Michael Niewöhner | 5c25964 | 2021-09-25 00:40:52 +0200 | [diff] [blame] | 114 | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE; |
| 115 | |
Michael Niewöhner | 586b1be | 2021-09-27 23:08:59 +0200 | [diff] [blame] | 116 | if (CONFIG(USE_PM_ACPI_TIMER)) |
Michael Niewöhner | 5c25964 | 2021-09-25 00:40:52 +0200 | [diff] [blame] | 117 | fadt->flags |= ACPI_FADT_PLATFORM_CLOCK; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 120 | unsigned long southbridge_write_acpi_tables(const struct device *device, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 121 | unsigned long current, |
| 122 | struct acpi_rsdp *rsdp) |
| 123 | { |
Marc Jones | 5258f4f | 2020-12-02 11:29:09 -0700 | [diff] [blame] | 124 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART)) { |
| 125 | current = acpi_write_dbg2_pci_uart(rsdp, current, |
| 126 | uart_get_device(), |
| 127 | ACPI_ACCESS_SIZE_DWORD_ACCESS); |
| 128 | } |
| 129 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 130 | return acpi_write_hpet(device, current, rsdp); |
| 131 | } |
| 132 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 133 | __weak |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 134 | void acpi_fill_soc_wake(uint32_t *pm1_en, uint32_t *gpe0_en, |
| 135 | const struct chipset_power_state *ps) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 136 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | /* |
| 140 | * Save wake source information for calculating ACPI _SWS values |
| 141 | * |
| 142 | * @pm1: PM1_STS register with only enabled events set |
| 143 | * @gpe0: GPE0_STS registers with only enabled events set |
| 144 | * |
Kyösti Mälkki | f67e6751 | 2021-01-22 19:59:07 +0200 | [diff] [blame] | 145 | * return the number of registers in the gpe0 array |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 146 | */ |
| 147 | |
Kyösti Mälkki | ca71e13 | 2021-01-15 05:06:35 +0200 | [diff] [blame] | 148 | int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 149 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 150 | static uint32_t gpe0_sts[GPE0_REG_MAX]; |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 151 | uint32_t gpe0_en[GPE0_REG_MAX]; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 152 | uint32_t pm1_en; |
| 153 | int i; |
| 154 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 155 | /* |
| 156 | * PM1_EN to check the basic wake events which can happen through |
| 157 | * powerbtn or any other wake source like lidopen, key board press etc. |
| 158 | */ |
| 159 | pm1_en = ps->pm1_en; |
Michael Niewöhner | f855b8b | 2021-10-10 16:56:31 +0200 | [diff] [blame] | 160 | pm1_en |= WAK_STS | PWRBTN_EN; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 161 | |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 162 | memcpy(gpe0_en, ps->gpe0_en, sizeof(gpe0_en)); |
| 163 | |
| 164 | acpi_fill_soc_wake(&pm1_en, gpe0_en, ps); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 165 | |
| 166 | *pm1 = ps->pm1_sts & pm1_en; |
| 167 | |
| 168 | /* Mask off GPE0 status bits that are not enabled */ |
| 169 | *gpe0 = &gpe0_sts[0]; |
| 170 | for (i = 0; i < GPE0_REG_MAX; i++) |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 171 | gpe0_sts[i] = ps->gpe0_sts[i] & gpe0_en[i]; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 172 | |
| 173 | return GPE0_REG_MAX; |
| 174 | } |
| 175 | |
Marc Jones | a81703c | 2020-12-18 10:44:47 -0700 | [diff] [blame] | 176 | int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 177 | { |
| 178 | u32 m; |
| 179 | u32 power; |
| 180 | |
| 181 | /* |
| 182 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 183 | * |
| 184 | * Power = (ratio / p1_ratio) * m * tdp |
| 185 | */ |
| 186 | |
| 187 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 188 | m = (m * m) / 1000; |
| 189 | |
| 190 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 191 | power *= (m / 100) * (tdp / 1000); |
| 192 | power /= 1000; |
| 193 | |
| 194 | return power; |
| 195 | } |
| 196 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 197 | static void generate_c_state_entries(void) |
| 198 | { |
Angel Pons | e9f10ff | 2021-10-17 13:28:23 +0200 | [diff] [blame] | 199 | const acpi_cstate_t *c_state_map; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 200 | size_t entries; |
| 201 | |
| 202 | c_state_map = soc_get_cstate_map(&entries); |
| 203 | |
| 204 | /* Generate C-state tables */ |
| 205 | acpigen_write_CST_package(c_state_map, entries); |
| 206 | } |
| 207 | |
| 208 | void generate_p_state_entries(int core, int cores_per_package) |
| 209 | { |
| 210 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 211 | int coord_type, power_max, num_entries; |
| 212 | int ratio, power, clock, clock_max; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 213 | bool turbo; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 214 | |
| 215 | coord_type = cpu_get_coord_type(); |
| 216 | ratio_min = cpu_get_min_ratio(); |
| 217 | ratio_max = cpu_get_max_ratio(); |
| 218 | clock_max = (ratio_max * cpu_get_bus_clock()) / KHz; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 219 | turbo = (get_turbo_state() == TURBO_ENABLED); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 220 | |
| 221 | /* Calculate CPU TDP in mW */ |
| 222 | power_max = cpu_get_power_max(); |
| 223 | |
| 224 | /* Write _PCT indicating use of FFixedHW */ |
| 225 | acpigen_write_empty_PCT(); |
| 226 | |
| 227 | /* Write _PPC with no limit on supported P-state */ |
| 228 | acpigen_write_PPC_NVS(); |
| 229 | /* Write PSD indicating configured coordination type */ |
| 230 | acpigen_write_PSD_package(core, 1, coord_type); |
| 231 | |
| 232 | /* Add P-state entries in _PSS table */ |
| 233 | acpigen_write_name("_PSS"); |
| 234 | |
| 235 | /* Determine ratio points */ |
| 236 | ratio_step = PSS_RATIO_STEP; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 237 | do { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 238 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 239 | if (((ratio_max - ratio_min) % ratio_step) > 0) |
| 240 | num_entries += 1; |
| 241 | if (turbo) |
| 242 | num_entries += 1; |
| 243 | if (num_entries > PSS_MAX_ENTRIES) |
| 244 | ratio_step += 1; |
| 245 | } while (num_entries > PSS_MAX_ENTRIES); |
| 246 | |
| 247 | /* _PSS package count depends on Turbo */ |
| 248 | acpigen_write_package(num_entries); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 249 | |
| 250 | /* P[T] is Turbo state if enabled */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 251 | if (turbo) { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 252 | ratio_turbo = cpu_get_max_turbo_ratio(); |
| 253 | |
| 254 | /* Add entry for Turbo ratio */ |
| 255 | acpigen_write_PSS_package(clock_max + 1, /* MHz */ |
| 256 | power_max, /* mW */ |
| 257 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 258 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 259 | ratio_turbo << 8, /* control */ |
| 260 | ratio_turbo << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 261 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | /* First regular entry is max non-turbo ratio */ |
| 265 | acpigen_write_PSS_package(clock_max, /* MHz */ |
| 266 | power_max, /* mW */ |
| 267 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 268 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 269 | ratio_max << 8, /* control */ |
| 270 | ratio_max << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 271 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 272 | |
| 273 | /* Generate the remaining entries */ |
| 274 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 275 | ratio >= ratio_min; ratio -= ratio_step) { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 276 | /* Calculate power at this ratio */ |
Marc Jones | a81703c | 2020-12-18 10:44:47 -0700 | [diff] [blame] | 277 | power = common_calculate_power_ratio(power_max, ratio_max, ratio); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 278 | clock = (ratio * cpu_get_bus_clock()) / KHz; |
| 279 | |
| 280 | acpigen_write_PSS_package(clock, /* MHz */ |
| 281 | power, /* mW */ |
| 282 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 283 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 284 | ratio << 8, /* control */ |
| 285 | ratio << 8); /* status */ |
| 286 | } |
| 287 | /* Fix package length */ |
| 288 | acpigen_pop_len(); |
| 289 | } |
| 290 | |
Elyes Haouas | feb683d | 2023-09-05 23:15:03 +0200 | [diff] [blame] | 291 | __weak acpi_tstate_t *soc_get_tss_table(int *entries) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 292 | { |
| 293 | *entries = 0; |
| 294 | return NULL; |
| 295 | } |
| 296 | |
| 297 | void generate_t_state_entries(int core, int cores_per_package) |
| 298 | { |
| 299 | acpi_tstate_t *soc_tss_table; |
| 300 | int entries; |
| 301 | |
| 302 | soc_tss_table = soc_get_tss_table(&entries); |
| 303 | if (entries == 0) |
| 304 | return; |
| 305 | |
| 306 | /* Indicate SW_ALL coordination for T-states */ |
| 307 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
| 308 | |
| 309 | /* Indicate FixedHW so OS will use MSR */ |
| 310 | acpigen_write_empty_PTC(); |
| 311 | |
| 312 | /* Set NVS controlled T-state limit */ |
| 313 | acpigen_write_TPC("\\TLVL"); |
| 314 | |
| 315 | /* Write TSS table for MSR access */ |
| 316 | acpigen_write_TSS_package(entries, soc_tss_table); |
| 317 | } |
| 318 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 319 | static void generate_cppc_entries(int core_id) |
| 320 | { |
Sridhar Siricilla | 1173612 | 2021-11-15 17:12:49 +0530 | [diff] [blame] | 321 | u32 version = CPPC_VERSION_2; |
| 322 | |
| 323 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) |
| 324 | version = CPPC_VERSION_3; |
| 325 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 326 | if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && |
| 327 | cpuid_eax(6) & CPUID_6_EAX_ISST)) |
| 328 | return; |
| 329 | |
| 330 | /* Generate GCPC package in first logical core */ |
| 331 | if (core_id == 0) { |
| 332 | struct cppc_config cppc_config; |
Sridhar Siricilla | 1173612 | 2021-11-15 17:12:49 +0530 | [diff] [blame] | 333 | cpu_init_cppc_config(&cppc_config, version); |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 334 | acpigen_write_CPPC_package(&cppc_config); |
| 335 | } |
| 336 | |
| 337 | /* Write _CPC entry for each logical core */ |
Sridhar Siricilla | 1173612 | 2021-11-15 17:12:49 +0530 | [diff] [blame] | 338 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) |
| 339 | acpigen_write_CPPC_hybrid_method(core_id); |
| 340 | else |
| 341 | acpigen_write_CPPC_method(); |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 342 | } |
| 343 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 344 | __weak void soc_power_states_generation(int core_id, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 345 | int cores_per_package) |
| 346 | { |
| 347 | } |
| 348 | |
Kyösti Mälkki | d521b96 | 2023-04-12 21:44:49 +0300 | [diff] [blame] | 349 | static void generate_cpu_entry(int cpu, int core, int cores_per_package) |
| 350 | { |
| 351 | /* Generate processor \_SB.CPUx */ |
| 352 | acpigen_write_processor_device(cpu * cores_per_package + core); |
| 353 | |
| 354 | /* Generate C-state tables */ |
| 355 | generate_c_state_entries(); |
| 356 | |
| 357 | generate_cppc_entries(core); |
| 358 | |
| 359 | /* Soc specific power states generation */ |
| 360 | soc_power_states_generation(core, cores_per_package); |
| 361 | |
| 362 | acpigen_write_processor_device_end(); |
| 363 | } |
| 364 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 365 | void generate_cpu_entries(const struct device *device) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 366 | { |
Michael Niewöhner | 2353cd9 | 2021-10-04 16:59:49 +0200 | [diff] [blame] | 367 | int core_id, cpu_id; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 368 | int totalcores = dev_count_cpu(); |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 369 | unsigned int num_virt; |
| 370 | unsigned int num_phys; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 371 | |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 372 | cpu_read_topology(&num_phys, &num_virt); |
| 373 | |
| 374 | int numcpus = totalcores / num_virt; |
| 375 | |
| 376 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d/%d physical/logical core(s) each.\n", |
| 377 | numcpus, num_phys, num_virt); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 378 | |
Kyösti Mälkki | d521b96 | 2023-04-12 21:44:49 +0300 | [diff] [blame] | 379 | for (cpu_id = 0; cpu_id < numcpus; cpu_id++) |
| 380 | for (core_id = 0; core_id < num_virt; core_id++) |
| 381 | generate_cpu_entry(cpu_id, core_id, num_virt); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 382 | |
Arthur Heymans | 0ac555e | 2018-11-28 12:25:54 +0100 | [diff] [blame] | 383 | /* PPKG is usually used for thermal management |
| 384 | of the first and only package. */ |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 385 | acpigen_write_processor_package("PPKG", 0, num_virt); |
Arthur Heymans | 0ac555e | 2018-11-28 12:25:54 +0100 | [diff] [blame] | 386 | |
| 387 | /* Add a method to notify processor nodes */ |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 388 | acpigen_write_processor_cnot(num_virt); |
Michael Niewöhner | b48caad | 2021-10-17 15:36:45 +0200 | [diff] [blame] | 389 | |
| 390 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) |
| 391 | sgx_fill_ssdt(); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 392 | } |
Marek Maslanka | 531c45e | 2024-01-12 07:24:21 +0000 | [diff] [blame] | 393 | |
| 394 | |
| 395 | static bool fill_wdat_timeout_entry(acpi_wdat_entry_t *entry) |
| 396 | { |
| 397 | uint16_t tcobase = tco_get_bar(); |
| 398 | |
| 399 | if (tcobase == 0) |
| 400 | return false; |
| 401 | |
| 402 | memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); |
| 403 | |
| 404 | entry->action = ACPI_WDAT_SET_COUNTDOWN; |
| 405 | entry->instruction = ACPI_WDAT_WRITE_COUNTDOWN | ACPI_WDAT_PRESERVE_REGISTER; |
| 406 | entry->mask = TCO_TMR_MASK; |
| 407 | entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; |
| 408 | entry->register_region.addrl = tcobase + TCO_TMR; |
| 409 | entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; |
| 410 | |
| 411 | return true; |
| 412 | } |
| 413 | |
| 414 | static bool fill_wdat_boot_status_entry(acpi_wdat_entry_t *entry, uint8_t action, |
| 415 | uint8_t instruction, uint32_t value) |
| 416 | { |
| 417 | uint16_t tcobase = tco_get_bar(); |
| 418 | |
| 419 | if (tcobase == 0) |
| 420 | return false; |
| 421 | |
| 422 | memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); |
| 423 | |
| 424 | entry->action = action; |
| 425 | entry->instruction = instruction; |
| 426 | entry->value = value; |
| 427 | entry->mask = TCO2_STS_SECOND_TO; |
| 428 | entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; |
| 429 | entry->register_region.addrl = tcobase + TCO_MESSAGE1; |
| 430 | entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_BYTE; |
| 431 | |
| 432 | return true; |
| 433 | } |
| 434 | |
| 435 | static bool fill_wdat_run_state_entry(acpi_wdat_entry_t *entry, uint8_t action, |
| 436 | uint8_t instruction, uint32_t value) |
| 437 | { |
| 438 | uint16_t tcobase = tco_get_bar(); |
| 439 | |
| 440 | if (tcobase == 0) |
| 441 | return false; |
| 442 | |
| 443 | memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); |
| 444 | |
| 445 | entry->action = action; |
| 446 | entry->instruction = instruction; |
| 447 | entry->value = value; |
| 448 | entry->mask = TCO1_TMR_HLT; |
| 449 | entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; |
| 450 | entry->register_region.addrl = tcobase + TCO1_CNT; |
| 451 | entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; |
| 452 | |
| 453 | return true; |
| 454 | } |
| 455 | |
| 456 | static bool fill_wdat_ping_entry(acpi_wdat_entry_t *entry) |
| 457 | { |
| 458 | uint16_t tcobase = tco_get_bar(); |
| 459 | |
| 460 | if (tcobase == 0) |
| 461 | return false; |
| 462 | |
| 463 | memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); |
| 464 | |
| 465 | entry->action = ACPI_WDAT_RESET; |
| 466 | entry->instruction = ACPI_WDAT_WRITE_VALUE; |
| 467 | entry->value = 0x01; |
| 468 | entry->mask = 0x01; |
| 469 | entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; |
| 470 | entry->register_region.addrl = tcobase + TCO_RLD; |
| 471 | entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; |
| 472 | |
| 473 | return true; |
| 474 | } |
| 475 | |
| 476 | unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) |
| 477 | { |
| 478 | if (!wdat) |
| 479 | return current; |
| 480 | |
| 481 | uint16_t tcobase = tco_get_bar(); |
| 482 | |
| 483 | if (tcobase == 0) |
| 484 | goto out_err; |
| 485 | |
| 486 | wdat->pci_segment = 0xff; |
| 487 | wdat->pci_bus = 0xff; |
| 488 | wdat->pci_device = 0xff; |
| 489 | wdat->pci_function = 0xff; |
| 490 | |
| 491 | wdat->timer_period = tco_get_timer_period(); |
| 492 | wdat->min_count = tco_get_timer_min_value(); |
| 493 | wdat->max_count = tco_get_timer_max_value(); |
| 494 | wdat->flags = ACPI_WDAT_FLAG_ENABLED; |
| 495 | wdat->entries = 0; |
| 496 | |
| 497 | acpi_wdat_entry_t *entry = (acpi_wdat_entry_t *)current; |
| 498 | |
| 499 | /* Write countdown */ |
| 500 | if (!fill_wdat_timeout_entry(entry)) |
| 501 | goto out_err; |
| 502 | |
| 503 | entry++; |
| 504 | |
| 505 | /* Get boot status */ |
| 506 | if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_GET_STATUS, |
| 507 | ACPI_WDAT_READ_VALUE, TCO2_STS_SECOND_TO)) |
| 508 | goto out_err; |
| 509 | |
| 510 | entry++; |
| 511 | |
| 512 | /* Set boot status */ |
| 513 | if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_SET_STATUS, |
| 514 | ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, |
| 515 | 0)) |
| 516 | goto out_err; |
| 517 | |
| 518 | entry++; |
| 519 | |
| 520 | /* Get running status */ |
| 521 | if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_RUNNING_STATE, |
| 522 | ACPI_WDAT_READ_VALUE, 0)) |
| 523 | goto out_err; |
| 524 | |
| 525 | entry++; |
| 526 | |
| 527 | /* Start the watchdog */ |
| 528 | if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_RUNNING_STATE, |
| 529 | ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, |
| 530 | 0)) |
| 531 | goto out_err; |
| 532 | |
| 533 | entry++; |
| 534 | |
| 535 | /* Get stopped status */ |
| 536 | if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_STOPPED_STATE, |
| 537 | ACPI_WDAT_READ_VALUE, TCO1_TMR_HLT)) |
| 538 | goto out_err; |
| 539 | |
| 540 | entry++; |
| 541 | |
| 542 | /* Stop the watchdog */ |
| 543 | if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_STOPPED_STATE, |
| 544 | ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, |
| 545 | TCO1_TMR_HLT)) |
| 546 | goto out_err; |
| 547 | |
| 548 | entry++; |
| 549 | |
| 550 | /* Ping */ |
| 551 | if (!fill_wdat_ping_entry(entry)) |
| 552 | goto out_err; |
| 553 | |
| 554 | entry++; |
| 555 | |
| 556 | wdat->entries = ((unsigned long)entry - current) / sizeof(acpi_wdat_entry_t); |
| 557 | |
| 558 | return (unsigned long)entry; |
| 559 | |
| 560 | out_err: |
| 561 | wdat->flags = ACPI_WDAT_FLAG_DISABLED; |
| 562 | printk(BIOS_ERR, "Fail to populate WDAT ACPI Table"); |
| 563 | |
| 564 | return current; |
| 565 | } |