Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpigen.h> |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame^] | 4 | #include <arch/cpu.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 5 | #include <arch/ioapic.h> |
| 6 | #include <arch/smp/mpspec.h> |
| 7 | #include <bootstate.h> |
| 8 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 9 | #include <cf9_reset.h> |
Kyösti Mälkki | 5daa1d3 | 2020-06-14 12:01:58 +0300 | [diff] [blame] | 10 | #include <acpi/acpi_gnvs.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 11 | #include <console/console.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 12 | #include <cpu/intel/turbo.h> |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame^] | 13 | #include <cpu/intel/common/common.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 14 | #include <cpu/x86/smm.h> |
| 15 | #include <intelblocks/acpi.h> |
| 16 | #include <intelblocks/msr.h> |
| 17 | #include <intelblocks/pmclib.h> |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 18 | #include <intelblocks/uart.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 19 | #include <soc/gpio.h> |
| 20 | #include <soc/iomap.h> |
| 21 | #include <soc/nvs.h> |
| 22 | #include <soc/pm.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 23 | #include <string.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 24 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame^] | 25 | #define CPUID_6_EAX_ISST (1 << 7) |
| 26 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame] | 27 | __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 28 | { |
| 29 | /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ |
| 30 | current += acpi_create_mcfg_mmconfig((void *)current, |
| 31 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, |
Duncan Laurie | fd50b7c | 2018-03-02 14:47:11 -0800 | [diff] [blame] | 32 | (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 33 | return current; |
| 34 | } |
| 35 | |
| 36 | static int acpi_sci_irq(void) |
| 37 | { |
| 38 | int sci_irq = 9; |
| 39 | uint32_t scis; |
| 40 | |
| 41 | scis = soc_read_sci_irq_select(); |
| 42 | scis &= SCI_IRQ_SEL; |
| 43 | scis >>= SCI_IRQ_ADJUST; |
| 44 | |
| 45 | /* Determine how SCI is routed. */ |
| 46 | switch (scis) { |
| 47 | case SCIS_IRQ9: |
| 48 | case SCIS_IRQ10: |
| 49 | case SCIS_IRQ11: |
| 50 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 51 | break; |
| 52 | case SCIS_IRQ20: |
| 53 | case SCIS_IRQ21: |
| 54 | case SCIS_IRQ22: |
| 55 | case SCIS_IRQ23: |
| 56 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 57 | break; |
| 58 | default: |
| 59 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); |
| 60 | sci_irq = 9; |
| 61 | break; |
| 62 | } |
| 63 | |
| 64 | printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); |
| 65 | return sci_irq; |
| 66 | } |
| 67 | |
| 68 | static unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 69 | { |
| 70 | int sci = acpi_sci_irq(); |
| 71 | uint16_t flags = MP_IRQ_TRIGGER_LEVEL; |
| 72 | |
| 73 | /* INT_SRC_OVR */ |
| 74 | current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); |
| 75 | |
| 76 | flags |= soc_madt_sci_irq_polarity(sci); |
| 77 | |
| 78 | /* SCI */ |
| 79 | current += |
| 80 | acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); |
| 81 | |
| 82 | return current; |
| 83 | } |
| 84 | |
| 85 | unsigned long acpi_fill_madt(unsigned long current) |
| 86 | { |
| 87 | /* Local APICs */ |
| 88 | current = acpi_create_madt_lapics(current); |
| 89 | |
| 90 | /* IOAPIC */ |
| 91 | current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); |
| 92 | |
| 93 | return acpi_madt_irq_overrides(current); |
| 94 | } |
| 95 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 96 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 97 | { |
| 98 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 99 | |
Marc Jones | f9ea7ed | 2018-08-22 18:59:26 -0600 | [diff] [blame] | 100 | fadt->header.revision = get_acpi_table_revision(FADT); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 101 | |
| 102 | fadt->sci_int = acpi_sci_irq(); |
Kyösti Mälkki | c328a68 | 2019-11-23 07:23:40 +0200 | [diff] [blame] | 103 | |
Kyösti Mälkki | 0a9e72e | 2019-08-11 01:22:28 +0300 | [diff] [blame] | 104 | if (permanent_smi_handler()) { |
Kyösti Mälkki | c328a68 | 2019-11-23 07:23:40 +0200 | [diff] [blame] | 105 | fadt->smi_cmd = APM_CNT; |
| 106 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 107 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 108 | } |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 109 | |
| 110 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 111 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 112 | |
| 113 | fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| 114 | |
| 115 | fadt->pm1_evt_len = 4; |
| 116 | fadt->pm1_cnt_len = 2; |
| 117 | |
| 118 | /* GPE0 STS/EN pairs each 32 bits wide. */ |
| 119 | fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); |
| 120 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 121 | fadt->duty_offset = 1; |
| 122 | fadt->day_alrm = 0xd; |
| 123 | |
Angel Pons | a208c6c | 2020-07-13 00:02:34 +0200 | [diff] [blame] | 124 | fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 125 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
Angel Pons | 79572e4 | 2020-07-13 00:17:43 +0200 | [diff] [blame] | 126 | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | |
| 127 | ACPI_FADT_PLATFORM_CLOCK; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 128 | |
Elyes HAOUAS | 04071f4 | 2020-07-20 17:05:24 +0200 | [diff] [blame] | 129 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 130 | fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
| 131 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
Angel Pons | 12a4d05 | 2020-07-14 01:31:27 +0200 | [diff] [blame] | 132 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 133 | |
Elyes HAOUAS | 04071f4 | 2020-07-20 17:05:24 +0200 | [diff] [blame] | 134 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 135 | fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
| 136 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 137 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 138 | |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 139 | /* |
| 140 | * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. |
| 141 | * The bit_width field intentionally overflows here. |
| 142 | * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which |
| 143 | * seems to work fine on Linux 5.0 and Windows 10. |
| 144 | */ |
| 145 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 146 | fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; |
| 147 | fadt->x_gpe0_blk.bit_offset = 0; |
Angel Pons | a23aff3 | 2020-06-21 20:47:54 +0200 | [diff] [blame] | 148 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 149 | fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
| 150 | fadt->x_gpe0_blk.addrh = 0; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 153 | unsigned long southbridge_write_acpi_tables(const struct device *device, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 154 | unsigned long current, |
| 155 | struct acpi_rsdp *rsdp) |
| 156 | { |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 157 | current = acpi_write_dbg2_pci_uart(rsdp, current, |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 158 | uart_get_device(), |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 159 | ACPI_ACCESS_SIZE_DWORD_ACCESS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 160 | return acpi_write_hpet(device, current, rsdp); |
| 161 | } |
| 162 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 163 | __weak |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 164 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 165 | const struct chipset_power_state *ps) |
| 166 | { |
| 167 | return generic_pm1_en; |
| 168 | } |
| 169 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 170 | #if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 171 | /* |
| 172 | * Save wake source information for calculating ACPI _SWS values |
| 173 | * |
| 174 | * @pm1: PM1_STS register with only enabled events set |
| 175 | * @gpe0: GPE0_STS registers with only enabled events set |
| 176 | * |
| 177 | * return the number of registers in the gpe0 array or -1 if nothing |
| 178 | * is provided by this function. |
| 179 | */ |
| 180 | |
| 181 | static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0) |
| 182 | { |
| 183 | struct chipset_power_state *ps; |
| 184 | static uint32_t gpe0_sts[GPE0_REG_MAX]; |
| 185 | uint32_t pm1_en; |
| 186 | int i; |
| 187 | |
| 188 | ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 189 | if (ps == NULL) |
| 190 | return -1; |
| 191 | |
| 192 | /* |
| 193 | * PM1_EN to check the basic wake events which can happen through |
| 194 | * powerbtn or any other wake source like lidopen, key board press etc. |
| 195 | */ |
| 196 | pm1_en = ps->pm1_en; |
| 197 | |
| 198 | pm1_en = acpi_fill_soc_wake(pm1_en, ps); |
| 199 | |
| 200 | *pm1 = ps->pm1_sts & pm1_en; |
| 201 | |
| 202 | /* Mask off GPE0 status bits that are not enabled */ |
| 203 | *gpe0 = &gpe0_sts[0]; |
| 204 | for (i = 0; i < GPE0_REG_MAX; i++) |
| 205 | gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; |
| 206 | |
| 207 | return GPE0_REG_MAX; |
| 208 | } |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame] | 209 | #endif |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 210 | |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 211 | __weak void acpi_create_gnvs(struct global_nvs *gnvs) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 212 | { |
| 213 | } |
| 214 | |
Furquan Shaikh | 338fd9a | 2020-04-24 22:57:05 -0700 | [diff] [blame] | 215 | void southbridge_inject_dsdt(const struct device *device) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 216 | { |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 217 | struct global_nvs *gnvs; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 218 | |
| 219 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 220 | if (!gnvs) { |
| 221 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
| 222 | if (gnvs) |
| 223 | memset(gnvs, 0, sizeof(*gnvs)); |
| 224 | } |
| 225 | |
| 226 | if (gnvs) { |
| 227 | acpi_create_gnvs(gnvs); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 228 | /* And tell SMI about it */ |
Kyösti Mälkki | c3c5521 | 2020-06-17 10:34:26 +0300 | [diff] [blame] | 229 | apm_control(APM_CNT_GNVS_UPDATE); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 230 | |
| 231 | /* Add it to DSDT. */ |
| 232 | acpigen_write_scope("\\"); |
| 233 | acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); |
| 234 | acpigen_pop_len(); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 239 | { |
| 240 | u32 m; |
| 241 | u32 power; |
| 242 | |
| 243 | /* |
| 244 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 245 | * |
| 246 | * Power = (ratio / p1_ratio) * m * tdp |
| 247 | */ |
| 248 | |
| 249 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 250 | m = (m * m) / 1000; |
| 251 | |
| 252 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 253 | power *= (m / 100) * (tdp / 1000); |
| 254 | power /= 1000; |
| 255 | |
| 256 | return power; |
| 257 | } |
| 258 | |
| 259 | static int get_cores_per_package(void) |
| 260 | { |
| 261 | struct cpuinfo_x86 c; |
| 262 | struct cpuid_result result; |
| 263 | int cores = 1; |
| 264 | |
| 265 | get_fms(&c, cpuid_eax(1)); |
| 266 | if (c.x86 != 6) |
| 267 | return 1; |
| 268 | |
| 269 | result = cpuid_ext(0xb, 1); |
| 270 | cores = result.ebx & 0xff; |
| 271 | |
| 272 | return cores; |
| 273 | } |
| 274 | |
| 275 | static void generate_c_state_entries(void) |
| 276 | { |
| 277 | acpi_cstate_t *c_state_map; |
| 278 | size_t entries; |
| 279 | |
| 280 | c_state_map = soc_get_cstate_map(&entries); |
| 281 | |
| 282 | /* Generate C-state tables */ |
| 283 | acpigen_write_CST_package(c_state_map, entries); |
| 284 | } |
| 285 | |
| 286 | void generate_p_state_entries(int core, int cores_per_package) |
| 287 | { |
| 288 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 289 | int coord_type, power_max, num_entries; |
| 290 | int ratio, power, clock, clock_max; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 291 | bool turbo; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 292 | |
| 293 | coord_type = cpu_get_coord_type(); |
| 294 | ratio_min = cpu_get_min_ratio(); |
| 295 | ratio_max = cpu_get_max_ratio(); |
| 296 | clock_max = (ratio_max * cpu_get_bus_clock()) / KHz; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 297 | turbo = (get_turbo_state() == TURBO_ENABLED); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 298 | |
| 299 | /* Calculate CPU TDP in mW */ |
| 300 | power_max = cpu_get_power_max(); |
| 301 | |
| 302 | /* Write _PCT indicating use of FFixedHW */ |
| 303 | acpigen_write_empty_PCT(); |
| 304 | |
| 305 | /* Write _PPC with no limit on supported P-state */ |
| 306 | acpigen_write_PPC_NVS(); |
| 307 | /* Write PSD indicating configured coordination type */ |
| 308 | acpigen_write_PSD_package(core, 1, coord_type); |
| 309 | |
| 310 | /* Add P-state entries in _PSS table */ |
| 311 | acpigen_write_name("_PSS"); |
| 312 | |
| 313 | /* Determine ratio points */ |
| 314 | ratio_step = PSS_RATIO_STEP; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 315 | do { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 316 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 317 | if (((ratio_max - ratio_min) % ratio_step) > 0) |
| 318 | num_entries += 1; |
| 319 | if (turbo) |
| 320 | num_entries += 1; |
| 321 | if (num_entries > PSS_MAX_ENTRIES) |
| 322 | ratio_step += 1; |
| 323 | } while (num_entries > PSS_MAX_ENTRIES); |
| 324 | |
| 325 | /* _PSS package count depends on Turbo */ |
| 326 | acpigen_write_package(num_entries); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 327 | |
| 328 | /* P[T] is Turbo state if enabled */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 329 | if (turbo) { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 330 | ratio_turbo = cpu_get_max_turbo_ratio(); |
| 331 | |
| 332 | /* Add entry for Turbo ratio */ |
| 333 | acpigen_write_PSS_package(clock_max + 1, /* MHz */ |
| 334 | power_max, /* mW */ |
| 335 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 336 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 337 | ratio_turbo << 8, /* control */ |
| 338 | ratio_turbo << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 339 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 340 | } |
| 341 | |
| 342 | /* First regular entry is max non-turbo ratio */ |
| 343 | acpigen_write_PSS_package(clock_max, /* MHz */ |
| 344 | power_max, /* mW */ |
| 345 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 346 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 347 | ratio_max << 8, /* control */ |
| 348 | ratio_max << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 349 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 350 | |
| 351 | /* Generate the remaining entries */ |
| 352 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 353 | ratio >= ratio_min; ratio -= ratio_step) { |
| 354 | |
| 355 | /* Calculate power at this ratio */ |
| 356 | power = calculate_power(power_max, ratio_max, ratio); |
| 357 | clock = (ratio * cpu_get_bus_clock()) / KHz; |
| 358 | |
| 359 | acpigen_write_PSS_package(clock, /* MHz */ |
| 360 | power, /* mW */ |
| 361 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 362 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 363 | ratio << 8, /* control */ |
| 364 | ratio << 8); /* status */ |
| 365 | } |
| 366 | /* Fix package length */ |
| 367 | acpigen_pop_len(); |
| 368 | } |
| 369 | |
Julien Viard de Galbert | 595202c | 2018-03-29 14:01:01 +0200 | [diff] [blame] | 370 | __attribute__ ((weak)) acpi_tstate_t *soc_get_tss_table(int *entries) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 371 | { |
| 372 | *entries = 0; |
| 373 | return NULL; |
| 374 | } |
| 375 | |
| 376 | void generate_t_state_entries(int core, int cores_per_package) |
| 377 | { |
| 378 | acpi_tstate_t *soc_tss_table; |
| 379 | int entries; |
| 380 | |
| 381 | soc_tss_table = soc_get_tss_table(&entries); |
| 382 | if (entries == 0) |
| 383 | return; |
| 384 | |
| 385 | /* Indicate SW_ALL coordination for T-states */ |
| 386 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
| 387 | |
| 388 | /* Indicate FixedHW so OS will use MSR */ |
| 389 | acpigen_write_empty_PTC(); |
| 390 | |
| 391 | /* Set NVS controlled T-state limit */ |
| 392 | acpigen_write_TPC("\\TLVL"); |
| 393 | |
| 394 | /* Write TSS table for MSR access */ |
| 395 | acpigen_write_TSS_package(entries, soc_tss_table); |
| 396 | } |
| 397 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame^] | 398 | static void generate_cppc_entries(int core_id) |
| 399 | { |
| 400 | if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && |
| 401 | cpuid_eax(6) & CPUID_6_EAX_ISST)) |
| 402 | return; |
| 403 | |
| 404 | /* Generate GCPC package in first logical core */ |
| 405 | if (core_id == 0) { |
| 406 | struct cppc_config cppc_config; |
| 407 | cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); |
| 408 | acpigen_write_CPPC_package(&cppc_config); |
| 409 | } |
| 410 | |
| 411 | /* Write _CPC entry for each logical core */ |
| 412 | acpigen_write_CPPC_method(); |
| 413 | } |
| 414 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 415 | __weak void soc_power_states_generation(int core_id, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 416 | int cores_per_package) |
| 417 | { |
| 418 | } |
| 419 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 420 | void generate_cpu_entries(const struct device *device) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 421 | { |
| 422 | int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; |
| 423 | int plen = 6; |
| 424 | int totalcores = dev_count_cpu(); |
| 425 | int cores_per_package = get_cores_per_package(); |
| 426 | int numcpus = totalcores / cores_per_package; |
| 427 | |
| 428 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 429 | numcpus, cores_per_package); |
| 430 | |
| 431 | for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { |
| 432 | for (core_id = 0; core_id < cores_per_package; core_id++) { |
| 433 | if (core_id > 0) { |
| 434 | pcontrol_blk = 0; |
| 435 | plen = 0; |
| 436 | } |
| 437 | |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 438 | /* Generate processor \_SB.CPUx */ |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 439 | acpigen_write_processor((cpu_id) * cores_per_package + |
| 440 | core_id, pcontrol_blk, plen); |
| 441 | |
| 442 | /* Generate C-state tables */ |
| 443 | generate_c_state_entries(); |
| 444 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame^] | 445 | generate_cppc_entries(core_id); |
| 446 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 447 | /* Soc specific power states generation */ |
| 448 | soc_power_states_generation(core_id, cores_per_package); |
| 449 | |
| 450 | acpigen_pop_len(); |
| 451 | } |
| 452 | } |
Arthur Heymans | 0ac555e | 2018-11-28 12:25:54 +0100 | [diff] [blame] | 453 | /* PPKG is usually used for thermal management |
| 454 | of the first and only package. */ |
| 455 | acpigen_write_processor_package("PPKG", 0, cores_per_package); |
| 456 | |
| 457 | /* Add a method to notify processor nodes */ |
| 458 | acpigen_write_processor_cnot(cores_per_package); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 459 | } |
| 460 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 461 | #if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 462 | /* Save wake source data for ACPI _SWS methods in NVS */ |
| 463 | static void acpi_save_wake_source(void *unused) |
| 464 | { |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 465 | struct global_nvs *gnvs = acpi_get_gnvs(); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 466 | uint32_t pm1, *gpe0; |
| 467 | int gpe_reg, gpe_reg_count; |
| 468 | int reg_size = sizeof(uint32_t) * 8; |
| 469 | |
| 470 | if (!gnvs) |
| 471 | return; |
| 472 | |
| 473 | gnvs->pm1i = -1; |
| 474 | gnvs->gpei = -1; |
| 475 | |
| 476 | gpe_reg_count = acpi_fill_wake(&pm1, &gpe0); |
| 477 | if (gpe_reg_count < 0) |
| 478 | return; |
| 479 | |
| 480 | /* Scan for first set bit in PM1 */ |
| 481 | for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) { |
| 482 | if (pm1 & 1) |
| 483 | break; |
| 484 | pm1 >>= 1; |
| 485 | } |
| 486 | |
| 487 | /* If unable to determine then return -1 */ |
| 488 | if (gnvs->pm1i >= 16) |
| 489 | gnvs->pm1i = -1; |
| 490 | |
| 491 | /* Scan for first set bit in GPE registers */ |
| 492 | for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) { |
| 493 | uint32_t gpe = gpe0[gpe_reg]; |
| 494 | int start = gpe_reg * reg_size; |
| 495 | int end = start + reg_size; |
| 496 | |
| 497 | if (gpe == 0) { |
| 498 | if (!gnvs->gpei) |
| 499 | gnvs->gpei = end; |
| 500 | continue; |
| 501 | } |
| 502 | |
| 503 | for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { |
| 504 | if (gpe & 1) |
| 505 | break; |
| 506 | gpe >>= 1; |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | /* If unable to determine then return -1 */ |
| 511 | if (gnvs->gpei >= gpe_reg_count * reg_size) |
| 512 | gnvs->gpei = -1; |
| 513 | |
| 514 | printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", |
| 515 | (long long)gnvs->pm1i, (long long)gnvs->gpei); |
| 516 | } |
| 517 | |
| 518 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); |
| 519 | |
| 520 | #endif |