blob: e5d3fee33f15ad114549828a793a6b8c83d46c1b [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Elyes HAOUASa1e22b82019-03-18 22:49:36 +01002
Kyösti Mälkki3139c8d2020-06-28 16:33:33 +03003#include <acpi/acpi_gnvs.h>
Kyösti Mälkki27872372021-01-21 16:05:26 +02004#include <acpi/acpi_pm.h>
Furquan Shaikh76cedd22020-05-02 10:24:23 -07005#include <acpi/acpigen.h>
Michael Niewöhnered21df62020-09-19 00:08:45 +02006#include <arch/cpu.h>
Shaunak Sahabd427802017-07-18 00:19:33 -07007#include <arch/ioapic.h>
8#include <arch/smp/mpspec.h>
9#include <bootstate.h>
Patrick Rudolphf677d172018-10-01 19:17:11 +020010#include <cf9_reset.h>
Elyes HAOUAS20eaef02019-03-29 17:45:28 +010011#include <console/console.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070012#include <cpu/intel/turbo.h>
Michael Niewöhnerf0a44ae2021-01-01 21:04:09 +010013#include <cpu/intel/msr.h>
Michael Niewöhnered21df62020-09-19 00:08:45 +020014#include <cpu/intel/common/common.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070015#include <cpu/x86/smm.h>
16#include <intelblocks/acpi.h>
Marc Jones1403b912020-12-02 14:35:27 -070017#include <intelblocks/lpc_lib.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070018#include <intelblocks/pmclib.h>
Duncan Laurie93bbd412017-11-11 20:03:29 -080019#include <intelblocks/uart.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070020#include <soc/gpio.h>
21#include <soc/iomap.h>
22#include <soc/nvs.h>
23#include <soc/pm.h>
Elyes HAOUASa1e22b82019-03-18 22:49:36 +010024#include <string.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070025
Michael Niewöhnered21df62020-09-19 00:08:45 +020026#define CPUID_6_EAX_ISST (1 << 7)
27
Julien Viard de Galbertcf2b72f2018-04-05 11:24:45 +020028__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current)
Shaunak Sahabd427802017-07-18 00:19:33 -070029{
30 /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
31 current += acpi_create_mcfg_mmconfig((void *)current,
32 CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
Duncan Lauriefd50b7c2018-03-02 14:47:11 -080033 (CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
Shaunak Sahabd427802017-07-18 00:19:33 -070034 return current;
35}
36
37static int acpi_sci_irq(void)
38{
39 int sci_irq = 9;
40 uint32_t scis;
41
42 scis = soc_read_sci_irq_select();
43 scis &= SCI_IRQ_SEL;
44 scis >>= SCI_IRQ_ADJUST;
45
46 /* Determine how SCI is routed. */
47 switch (scis) {
48 case SCIS_IRQ9:
49 case SCIS_IRQ10:
50 case SCIS_IRQ11:
51 sci_irq = scis - SCIS_IRQ9 + 9;
52 break;
53 case SCIS_IRQ20:
54 case SCIS_IRQ21:
55 case SCIS_IRQ22:
56 case SCIS_IRQ23:
57 sci_irq = scis - SCIS_IRQ20 + 20;
58 break;
59 default:
60 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
61 sci_irq = 9;
62 break;
63 }
64
65 printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
66 return sci_irq;
67}
68
69static unsigned long acpi_madt_irq_overrides(unsigned long current)
70{
71 int sci = acpi_sci_irq();
72 uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
73
74 /* INT_SRC_OVR */
75 current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
76
77 flags |= soc_madt_sci_irq_polarity(sci);
78
79 /* SCI */
80 current +=
81 acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
82
Michael Niewöhner14512f92020-11-23 15:53:28 +010083 /* NMI */
84 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
85
Shaunak Sahabd427802017-07-18 00:19:33 -070086 return current;
87}
88
Marc Jones847043c2020-12-02 11:24:00 -070089__weak const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries)
90{
91 *entries = 0;
92 return NULL;
93}
94
Shaunak Sahabd427802017-07-18 00:19:33 -070095unsigned long acpi_fill_madt(unsigned long current)
96{
Marc Jones847043c2020-12-02 11:24:00 -070097 const struct madt_ioapic_info *ioapic_table;
98 size_t ioapic_entries;
99
Shaunak Sahabd427802017-07-18 00:19:33 -0700100 /* Local APICs */
101 current = acpi_create_madt_lapics(current);
102
103 /* IOAPIC */
Marc Jones847043c2020-12-02 11:24:00 -0700104 ioapic_table = soc_get_ioapic_info(&ioapic_entries);
105 if (ioapic_entries) {
106 for (int i = 0; i < ioapic_entries; i++) {
107 current += acpi_create_madt_ioapic(
108 (void *)current,
109 ioapic_table[i].id,
110 ioapic_table[i].addr,
111 ioapic_table[i].gsi_base);
112 }
113 } else {
114 /* Default SOC IOAPIC entry */
115 current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
116 }
Shaunak Sahabd427802017-07-18 00:19:33 -0700117
118 return acpi_madt_irq_overrides(current);
119}
120
Shaunak Sahabd427802017-07-18 00:19:33 -0700121void acpi_fill_fadt(acpi_fadt_t *fadt)
122{
123 const uint16_t pmbase = ACPI_BASE_ADDRESS;
124
Marc Jonesf9ea7ed2018-08-22 18:59:26 -0600125 fadt->header.revision = get_acpi_table_revision(FADT);
Shaunak Sahabd427802017-07-18 00:19:33 -0700126
127 fadt->sci_int = acpi_sci_irq();
Kyösti Mälkkic328a682019-11-23 07:23:40 +0200128
Kyösti Mälkki0a9e72e2019-08-11 01:22:28 +0300129 if (permanent_smi_handler()) {
Kyösti Mälkkic328a682019-11-23 07:23:40 +0200130 fadt->smi_cmd = APM_CNT;
131 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
132 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
133 }
Shaunak Sahabd427802017-07-18 00:19:33 -0700134
135 fadt->pm1a_evt_blk = pmbase + PM1_STS;
Shaunak Sahabd427802017-07-18 00:19:33 -0700136 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
Shaunak Sahabd427802017-07-18 00:19:33 -0700137
138 fadt->gpe0_blk = pmbase + GPE0_STS(0);
139
140 fadt->pm1_evt_len = 4;
141 fadt->pm1_cnt_len = 2;
142
143 /* GPE0 STS/EN pairs each 32 bits wide. */
144 fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
145
Shaunak Sahabd427802017-07-18 00:19:33 -0700146 fadt->duty_offset = 1;
147 fadt->day_alrm = 0xd;
148
Angel Ponsa208c6c2020-07-13 00:02:34 +0200149 fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
150 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
Angel Pons79572e42020-07-13 00:17:43 +0200151 ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
152 ACPI_FADT_PLATFORM_CLOCK;
Shaunak Sahabd427802017-07-18 00:19:33 -0700153
Elyes HAOUAS04071f42020-07-20 17:05:24 +0200154 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
Shaunak Sahabd427802017-07-18 00:19:33 -0700155 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
156 fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
Angel Pons12a4d052020-07-14 01:31:27 +0200157 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100158
Elyes HAOUAS04071f42020-07-20 17:05:24 +0200159 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
Shaunak Sahabd427802017-07-18 00:19:33 -0700160 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
161 fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100162 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
Shaunak Sahabd427802017-07-18 00:19:33 -0700163
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100164 /*
165 * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
166 * The bit_width field intentionally overflows here.
167 * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
168 * seems to work fine on Linux 5.0 and Windows 10.
169 */
170 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
171 fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
172 fadt->x_gpe0_blk.bit_offset = 0;
Angel Ponsa23aff32020-06-21 20:47:54 +0200173 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100174 fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
175 fadt->x_gpe0_blk.addrh = 0;
Shaunak Sahabd427802017-07-18 00:19:33 -0700176}
177
Furquan Shaikh0f007d82020-04-24 06:41:18 -0700178unsigned long southbridge_write_acpi_tables(const struct device *device,
Shaunak Sahabd427802017-07-18 00:19:33 -0700179 unsigned long current,
180 struct acpi_rsdp *rsdp)
181{
Marc Jones5258f4f2020-12-02 11:29:09 -0700182 if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART)) {
183 current = acpi_write_dbg2_pci_uart(rsdp, current,
184 uart_get_device(),
185 ACPI_ACCESS_SIZE_DWORD_ACCESS);
186 }
187
Shaunak Sahabd427802017-07-18 00:19:33 -0700188 return acpi_write_hpet(device, current, rsdp);
189}
190
Aaron Durbin64031672018-04-21 14:45:32 -0600191__weak
Shaunak Sahabd427802017-07-18 00:19:33 -0700192uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
193 const struct chipset_power_state *ps)
194{
195 return generic_pm1_en;
196}
197
Julius Wernercd49cce2019-03-05 16:53:33 -0800198#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
Shaunak Sahabd427802017-07-18 00:19:33 -0700199/*
200 * Save wake source information for calculating ACPI _SWS values
201 *
202 * @pm1: PM1_STS register with only enabled events set
203 * @gpe0: GPE0_STS registers with only enabled events set
204 *
Kyösti Mälkkif67e67512021-01-22 19:59:07 +0200205 * return the number of registers in the gpe0 array
Shaunak Sahabd427802017-07-18 00:19:33 -0700206 */
207
Kyösti Mälkkif67e67512021-01-22 19:59:07 +0200208static int acpi_fill_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0)
Shaunak Sahabd427802017-07-18 00:19:33 -0700209{
Shaunak Sahabd427802017-07-18 00:19:33 -0700210 static uint32_t gpe0_sts[GPE0_REG_MAX];
211 uint32_t pm1_en;
212 int i;
213
Shaunak Sahabd427802017-07-18 00:19:33 -0700214 /*
215 * PM1_EN to check the basic wake events which can happen through
216 * powerbtn or any other wake source like lidopen, key board press etc.
217 */
218 pm1_en = ps->pm1_en;
219
220 pm1_en = acpi_fill_soc_wake(pm1_en, ps);
221
222 *pm1 = ps->pm1_sts & pm1_en;
223
224 /* Mask off GPE0 status bits that are not enabled */
225 *gpe0 = &gpe0_sts[0];
226 for (i = 0; i < GPE0_REG_MAX; i++)
227 gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
228
229 return GPE0_REG_MAX;
230}
Julien Viard de Galbertcf2b72f2018-04-05 11:24:45 +0200231#endif
Shaunak Sahabd427802017-07-18 00:19:33 -0700232
Marc Jonesa81703c2020-12-18 10:44:47 -0700233int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio)
Shaunak Sahabd427802017-07-18 00:19:33 -0700234{
235 u32 m;
236 u32 power;
237
238 /*
239 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
240 *
241 * Power = (ratio / p1_ratio) * m * tdp
242 */
243
244 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
245 m = (m * m) / 1000;
246
247 power = ((ratio * 100000 / p1_ratio) / 100);
248 power *= (m / 100) * (tdp / 1000);
249 power /= 1000;
250
251 return power;
252}
253
Shaunak Sahabd427802017-07-18 00:19:33 -0700254static void generate_c_state_entries(void)
255{
256 acpi_cstate_t *c_state_map;
257 size_t entries;
258
259 c_state_map = soc_get_cstate_map(&entries);
260
261 /* Generate C-state tables */
262 acpigen_write_CST_package(c_state_map, entries);
263}
264
265void generate_p_state_entries(int core, int cores_per_package)
266{
267 int ratio_min, ratio_max, ratio_turbo, ratio_step;
268 int coord_type, power_max, num_entries;
269 int ratio, power, clock, clock_max;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100270 bool turbo;
Shaunak Sahabd427802017-07-18 00:19:33 -0700271
272 coord_type = cpu_get_coord_type();
273 ratio_min = cpu_get_min_ratio();
274 ratio_max = cpu_get_max_ratio();
275 clock_max = (ratio_max * cpu_get_bus_clock()) / KHz;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100276 turbo = (get_turbo_state() == TURBO_ENABLED);
Shaunak Sahabd427802017-07-18 00:19:33 -0700277
278 /* Calculate CPU TDP in mW */
279 power_max = cpu_get_power_max();
280
281 /* Write _PCT indicating use of FFixedHW */
282 acpigen_write_empty_PCT();
283
284 /* Write _PPC with no limit on supported P-state */
285 acpigen_write_PPC_NVS();
286 /* Write PSD indicating configured coordination type */
287 acpigen_write_PSD_package(core, 1, coord_type);
288
289 /* Add P-state entries in _PSS table */
290 acpigen_write_name("_PSS");
291
292 /* Determine ratio points */
293 ratio_step = PSS_RATIO_STEP;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100294 do {
Shaunak Sahabd427802017-07-18 00:19:33 -0700295 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100296 if (((ratio_max - ratio_min) % ratio_step) > 0)
297 num_entries += 1;
298 if (turbo)
299 num_entries += 1;
300 if (num_entries > PSS_MAX_ENTRIES)
301 ratio_step += 1;
302 } while (num_entries > PSS_MAX_ENTRIES);
303
304 /* _PSS package count depends on Turbo */
305 acpigen_write_package(num_entries);
Shaunak Sahabd427802017-07-18 00:19:33 -0700306
307 /* P[T] is Turbo state if enabled */
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100308 if (turbo) {
Shaunak Sahabd427802017-07-18 00:19:33 -0700309 ratio_turbo = cpu_get_max_turbo_ratio();
310
311 /* Add entry for Turbo ratio */
312 acpigen_write_PSS_package(clock_max + 1, /* MHz */
313 power_max, /* mW */
314 PSS_LATENCY_TRANSITION,/* lat1 */
315 PSS_LATENCY_BUSMASTER,/* lat2 */
316 ratio_turbo << 8, /* control */
317 ratio_turbo << 8); /* status */
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100318 num_entries -= 1;
Shaunak Sahabd427802017-07-18 00:19:33 -0700319 }
320
321 /* First regular entry is max non-turbo ratio */
322 acpigen_write_PSS_package(clock_max, /* MHz */
323 power_max, /* mW */
324 PSS_LATENCY_TRANSITION,/* lat1 */
325 PSS_LATENCY_BUSMASTER,/* lat2 */
326 ratio_max << 8, /* control */
327 ratio_max << 8); /* status */
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100328 num_entries -= 1;
Shaunak Sahabd427802017-07-18 00:19:33 -0700329
330 /* Generate the remaining entries */
331 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
332 ratio >= ratio_min; ratio -= ratio_step) {
333
334 /* Calculate power at this ratio */
Marc Jonesa81703c2020-12-18 10:44:47 -0700335 power = common_calculate_power_ratio(power_max, ratio_max, ratio);
Shaunak Sahabd427802017-07-18 00:19:33 -0700336 clock = (ratio * cpu_get_bus_clock()) / KHz;
337
338 acpigen_write_PSS_package(clock, /* MHz */
339 power, /* mW */
340 PSS_LATENCY_TRANSITION,/* lat1 */
341 PSS_LATENCY_BUSMASTER,/* lat2 */
342 ratio << 8, /* control */
343 ratio << 8); /* status */
344 }
345 /* Fix package length */
346 acpigen_pop_len();
347}
348
Julien Viard de Galbert595202c2018-03-29 14:01:01 +0200349__attribute__ ((weak)) acpi_tstate_t *soc_get_tss_table(int *entries)
Shaunak Sahabd427802017-07-18 00:19:33 -0700350{
351 *entries = 0;
352 return NULL;
353}
354
355void generate_t_state_entries(int core, int cores_per_package)
356{
357 acpi_tstate_t *soc_tss_table;
358 int entries;
359
360 soc_tss_table = soc_get_tss_table(&entries);
361 if (entries == 0)
362 return;
363
364 /* Indicate SW_ALL coordination for T-states */
365 acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
366
367 /* Indicate FixedHW so OS will use MSR */
368 acpigen_write_empty_PTC();
369
370 /* Set NVS controlled T-state limit */
371 acpigen_write_TPC("\\TLVL");
372
373 /* Write TSS table for MSR access */
374 acpigen_write_TSS_package(entries, soc_tss_table);
375}
376
Michael Niewöhnered21df62020-09-19 00:08:45 +0200377static void generate_cppc_entries(int core_id)
378{
379 if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) &&
380 cpuid_eax(6) & CPUID_6_EAX_ISST))
381 return;
382
383 /* Generate GCPC package in first logical core */
384 if (core_id == 0) {
385 struct cppc_config cppc_config;
386 cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2);
387 acpigen_write_CPPC_package(&cppc_config);
388 }
389
390 /* Write _CPC entry for each logical core */
391 acpigen_write_CPPC_method();
392}
393
Aaron Durbin64031672018-04-21 14:45:32 -0600394__weak void soc_power_states_generation(int core_id,
Shaunak Sahabd427802017-07-18 00:19:33 -0700395 int cores_per_package)
396{
397}
398
Furquan Shaikh7536a392020-04-24 21:59:21 -0700399void generate_cpu_entries(const struct device *device)
Shaunak Sahabd427802017-07-18 00:19:33 -0700400{
401 int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
402 int plen = 6;
403 int totalcores = dev_count_cpu();
Patrick Rudolph7a66ffb2020-12-17 14:42:29 +0100404 unsigned int num_virt;
405 unsigned int num_phys;
Shaunak Sahabd427802017-07-18 00:19:33 -0700406
Patrick Rudolph7a66ffb2020-12-17 14:42:29 +0100407 cpu_read_topology(&num_phys, &num_virt);
408
409 int numcpus = totalcores / num_virt;
410
411 printk(BIOS_DEBUG, "Found %d CPU(s) with %d/%d physical/logical core(s) each.\n",
412 numcpus, num_phys, num_virt);
Shaunak Sahabd427802017-07-18 00:19:33 -0700413
414 for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
Patrick Rudolph7a66ffb2020-12-17 14:42:29 +0100415 for (core_id = 0; core_id < num_virt; core_id++) {
Shaunak Sahabd427802017-07-18 00:19:33 -0700416 if (core_id > 0) {
417 pcontrol_blk = 0;
418 plen = 0;
419 }
420
Christian Walterbe3979c2019-12-18 15:07:59 +0100421 /* Generate processor \_SB.CPUx */
Patrick Rudolph7a66ffb2020-12-17 14:42:29 +0100422 acpigen_write_processor((cpu_id) * num_virt +
Shaunak Sahabd427802017-07-18 00:19:33 -0700423 core_id, pcontrol_blk, plen);
424
425 /* Generate C-state tables */
426 generate_c_state_entries();
427
Michael Niewöhnered21df62020-09-19 00:08:45 +0200428 generate_cppc_entries(core_id);
429
Shaunak Sahabd427802017-07-18 00:19:33 -0700430 /* Soc specific power states generation */
Patrick Rudolph7a66ffb2020-12-17 14:42:29 +0100431 soc_power_states_generation(core_id, num_virt);
Shaunak Sahabd427802017-07-18 00:19:33 -0700432
433 acpigen_pop_len();
434 }
435 }
Arthur Heymans0ac555e2018-11-28 12:25:54 +0100436 /* PPKG is usually used for thermal management
437 of the first and only package. */
Patrick Rudolph7a66ffb2020-12-17 14:42:29 +0100438 acpigen_write_processor_package("PPKG", 0, num_virt);
Arthur Heymans0ac555e2018-11-28 12:25:54 +0100439
440 /* Add a method to notify processor nodes */
Patrick Rudolph7a66ffb2020-12-17 14:42:29 +0100441 acpigen_write_processor_cnot(num_virt);
Shaunak Sahabd427802017-07-18 00:19:33 -0700442}
443
Julius Wernercd49cce2019-03-05 16:53:33 -0800444#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
Shaunak Sahabd427802017-07-18 00:19:33 -0700445/* Save wake source data for ACPI _SWS methods in NVS */
446static void acpi_save_wake_source(void *unused)
447{
Kyösti Mälkki0c1dd9c2020-06-17 23:37:49 +0300448 struct global_nvs *gnvs = acpi_get_gnvs();
Shaunak Sahabd427802017-07-18 00:19:33 -0700449 uint32_t pm1, *gpe0;
450 int gpe_reg, gpe_reg_count;
451 int reg_size = sizeof(uint32_t) * 8;
452
453 if (!gnvs)
454 return;
455
456 gnvs->pm1i = -1;
457 gnvs->gpei = -1;
458
Kyösti Mälkkif67e67512021-01-22 19:59:07 +0200459 const struct chipset_power_state *ps = acpi_get_pm_state();
460 if (!ps)
461 return;
462
463 gpe_reg_count = acpi_fill_wake(ps, &pm1, &gpe0);
Shaunak Sahabd427802017-07-18 00:19:33 -0700464 if (gpe_reg_count < 0)
465 return;
466
467 /* Scan for first set bit in PM1 */
468 for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) {
469 if (pm1 & 1)
470 break;
471 pm1 >>= 1;
472 }
473
474 /* If unable to determine then return -1 */
475 if (gnvs->pm1i >= 16)
476 gnvs->pm1i = -1;
477
478 /* Scan for first set bit in GPE registers */
479 for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) {
480 uint32_t gpe = gpe0[gpe_reg];
481 int start = gpe_reg * reg_size;
482 int end = start + reg_size;
483
484 if (gpe == 0) {
485 if (!gnvs->gpei)
486 gnvs->gpei = end;
487 continue;
488 }
489
490 for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
491 if (gpe & 1)
492 break;
493 gpe >>= 1;
494 }
495 }
496
497 /* If unable to determine then return -1 */
498 if (gnvs->gpei >= gpe_reg_count * reg_size)
499 gnvs->gpei = -1;
500
501 printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
502 (long long)gnvs->pm1i, (long long)gnvs->gpei);
503}
504
505BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL);
506
507#endif