Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 2 | |
Eran Mitrani | 4c9440c | 2022-11-29 17:46:38 -0800 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 4 | #include <acpi/acpi_pm.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpigen.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 6 | #include <arch/ioapic.h> |
| 7 | #include <arch/smp/mpspec.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 8 | #include <console/console.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 9 | #include <cpu/cpu.h> |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 10 | #include <cpu/intel/common/common.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 11 | #include <cpu/intel/msr.h> |
| 12 | #include <cpu/intel/turbo.h> |
| 13 | #include <cpu/x86/lapic.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 14 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | ca71e13 | 2021-01-15 05:06:35 +0200 | [diff] [blame] | 15 | #include <intelblocks/acpi_wake_source.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 16 | #include <intelblocks/acpi.h> |
Marc Jones | 1403b91 | 2020-12-02 14:35:27 -0700 | [diff] [blame] | 17 | #include <intelblocks/lpc_lib.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 18 | #include <intelblocks/pmclib.h> |
Michael Niewöhner | b48caad | 2021-10-17 15:36:45 +0200 | [diff] [blame] | 19 | #include <intelblocks/sgx.h> |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 20 | #include <intelblocks/uart.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 21 | #include <soc/gpio.h> |
| 22 | #include <soc/iomap.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 23 | #include <soc/pm.h> |
| 24 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 25 | #define CPUID_6_EAX_ISST (1 << 7) |
| 26 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 27 | static int acpi_sci_irq(void) |
| 28 | { |
| 29 | int sci_irq = 9; |
| 30 | uint32_t scis; |
| 31 | |
| 32 | scis = soc_read_sci_irq_select(); |
| 33 | scis &= SCI_IRQ_SEL; |
| 34 | scis >>= SCI_IRQ_ADJUST; |
| 35 | |
| 36 | /* Determine how SCI is routed. */ |
| 37 | switch (scis) { |
| 38 | case SCIS_IRQ9: |
| 39 | case SCIS_IRQ10: |
| 40 | case SCIS_IRQ11: |
| 41 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 42 | break; |
| 43 | case SCIS_IRQ20: |
| 44 | case SCIS_IRQ21: |
| 45 | case SCIS_IRQ22: |
| 46 | case SCIS_IRQ23: |
| 47 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 48 | break; |
| 49 | default: |
| 50 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); |
| 51 | sci_irq = 9; |
| 52 | break; |
| 53 | } |
| 54 | |
| 55 | printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); |
| 56 | return sci_irq; |
| 57 | } |
| 58 | |
| 59 | static unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 60 | { |
| 61 | int sci = acpi_sci_irq(); |
| 62 | uint16_t flags = MP_IRQ_TRIGGER_LEVEL; |
| 63 | |
| 64 | /* INT_SRC_OVR */ |
| 65 | current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); |
| 66 | |
| 67 | flags |= soc_madt_sci_irq_polarity(sci); |
| 68 | |
| 69 | /* SCI */ |
| 70 | current += |
| 71 | acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); |
| 72 | |
| 73 | return current; |
| 74 | } |
| 75 | |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 76 | static const uintptr_t default_ioapic_bases[] = { IO_APIC_ADDR }; |
| 77 | |
| 78 | __weak size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) |
Marc Jones | 847043c | 2020-12-02 11:24:00 -0700 | [diff] [blame] | 79 | { |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 80 | *ioapic_bases = default_ioapic_bases; |
| 81 | return ARRAY_SIZE(default_ioapic_bases); |
Marc Jones | 847043c | 2020-12-02 11:24:00 -0700 | [diff] [blame] | 82 | } |
| 83 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 84 | unsigned long acpi_fill_madt(unsigned long current) |
| 85 | { |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 86 | const uintptr_t *ioapic_table; |
Marc Jones | 847043c | 2020-12-02 11:24:00 -0700 | [diff] [blame] | 87 | size_t ioapic_entries; |
| 88 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 89 | /* Local APICs */ |
Kyösti Mälkki | 69a1396 | 2023-04-08 14:10:48 +0300 | [diff] [blame^] | 90 | if (!CONFIG(ACPI_COMMON_MADT_LAPIC)) |
Sridhar Siricilla | 7301cfa | 2023-01-19 18:50:09 +0530 | [diff] [blame] | 91 | current = acpi_create_madt_lapics_with_nmis_hybrid(current); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 92 | |
| 93 | /* IOAPIC */ |
Arthur Heymans | 8a3e2b8 | 2022-12-02 12:42:27 +0100 | [diff] [blame] | 94 | ioapic_entries = soc_get_ioapic_info(&ioapic_table); |
| 95 | for (int i = 0; i < ioapic_entries; i++) |
| 96 | current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 97 | |
| 98 | return acpi_madt_irq_overrides(current); |
| 99 | } |
| 100 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 101 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 102 | { |
| 103 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 104 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 105 | fadt->sci_int = acpi_sci_irq(); |
Kyösti Mälkki | c328a68 | 2019-11-23 07:23:40 +0200 | [diff] [blame] | 106 | |
Kyösti Mälkki | 0a9e72e | 2019-08-11 01:22:28 +0300 | [diff] [blame] | 107 | if (permanent_smi_handler()) { |
Kyösti Mälkki | c328a68 | 2019-11-23 07:23:40 +0200 | [diff] [blame] | 108 | fadt->smi_cmd = APM_CNT; |
| 109 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 110 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 111 | } |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 112 | |
| 113 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 114 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 115 | |
| 116 | fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| 117 | |
| 118 | fadt->pm1_evt_len = 4; |
| 119 | fadt->pm1_cnt_len = 2; |
| 120 | |
| 121 | /* GPE0 STS/EN pairs each 32 bits wide. */ |
| 122 | fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); |
| 123 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 124 | fadt->day_alrm = 0xd; |
| 125 | |
Angel Pons | a208c6c | 2020-07-13 00:02:34 +0200 | [diff] [blame] | 126 | fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
Michael Niewöhner | 2353cd9 | 2021-10-04 16:59:49 +0200 | [diff] [blame] | 127 | ACPI_FADT_SLEEP_BUTTON | |
Michael Niewöhner | 5c25964 | 2021-09-25 00:40:52 +0200 | [diff] [blame] | 128 | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE; |
| 129 | |
Michael Niewöhner | 586b1be | 2021-09-27 23:08:59 +0200 | [diff] [blame] | 130 | if (CONFIG(USE_PM_ACPI_TIMER)) |
Michael Niewöhner | 5c25964 | 2021-09-25 00:40:52 +0200 | [diff] [blame] | 131 | fadt->flags |= ACPI_FADT_PLATFORM_CLOCK; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 132 | |
Elyes HAOUAS | 04071f4 | 2020-07-20 17:05:24 +0200 | [diff] [blame] | 133 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 134 | fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
Felix Held | 769b657 | 2022-10-14 18:32:52 +0200 | [diff] [blame] | 135 | fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; |
Angel Pons | 12a4d05 | 2020-07-14 01:31:27 +0200 | [diff] [blame] | 136 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 137 | |
Elyes HAOUAS | 04071f4 | 2020-07-20 17:05:24 +0200 | [diff] [blame] | 138 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 139 | fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
Elyes Haouas | c60f3b2 | 2022-10-11 14:02:27 +0200 | [diff] [blame] | 140 | fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 141 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 142 | |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 143 | /* |
| 144 | * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. |
| 145 | * The bit_width field intentionally overflows here. |
| 146 | * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which |
| 147 | * seems to work fine on Linux 5.0 and Windows 10. |
| 148 | */ |
| 149 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 150 | fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; |
| 151 | fadt->x_gpe0_blk.bit_offset = 0; |
Angel Pons | a23aff3 | 2020-06-21 20:47:54 +0200 | [diff] [blame] | 152 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 153 | fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
| 154 | fadt->x_gpe0_blk.addrh = 0; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 155 | } |
| 156 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 157 | unsigned long southbridge_write_acpi_tables(const struct device *device, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 158 | unsigned long current, |
| 159 | struct acpi_rsdp *rsdp) |
| 160 | { |
Marc Jones | 5258f4f | 2020-12-02 11:29:09 -0700 | [diff] [blame] | 161 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART)) { |
| 162 | current = acpi_write_dbg2_pci_uart(rsdp, current, |
| 163 | uart_get_device(), |
| 164 | ACPI_ACCESS_SIZE_DWORD_ACCESS); |
| 165 | } |
| 166 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 167 | return acpi_write_hpet(device, current, rsdp); |
| 168 | } |
| 169 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 170 | __weak |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 171 | void acpi_fill_soc_wake(uint32_t *pm1_en, uint32_t *gpe0_en, |
| 172 | const struct chipset_power_state *ps) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 173 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | /* |
| 177 | * Save wake source information for calculating ACPI _SWS values |
| 178 | * |
| 179 | * @pm1: PM1_STS register with only enabled events set |
| 180 | * @gpe0: GPE0_STS registers with only enabled events set |
| 181 | * |
Kyösti Mälkki | f67e6751 | 2021-01-22 19:59:07 +0200 | [diff] [blame] | 182 | * return the number of registers in the gpe0 array |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 183 | */ |
| 184 | |
Kyösti Mälkki | ca71e13 | 2021-01-15 05:06:35 +0200 | [diff] [blame] | 185 | int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 186 | { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 187 | static uint32_t gpe0_sts[GPE0_REG_MAX]; |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 188 | uint32_t gpe0_en[GPE0_REG_MAX]; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 189 | uint32_t pm1_en; |
| 190 | int i; |
| 191 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 192 | /* |
| 193 | * PM1_EN to check the basic wake events which can happen through |
| 194 | * powerbtn or any other wake source like lidopen, key board press etc. |
| 195 | */ |
| 196 | pm1_en = ps->pm1_en; |
Michael Niewöhner | f855b8b | 2021-10-10 16:56:31 +0200 | [diff] [blame] | 197 | pm1_en |= WAK_STS | PWRBTN_EN; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 198 | |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 199 | memcpy(gpe0_en, ps->gpe0_en, sizeof(gpe0_en)); |
| 200 | |
| 201 | acpi_fill_soc_wake(&pm1_en, gpe0_en, ps); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 202 | |
| 203 | *pm1 = ps->pm1_sts & pm1_en; |
| 204 | |
| 205 | /* Mask off GPE0 status bits that are not enabled */ |
| 206 | *gpe0 = &gpe0_sts[0]; |
| 207 | for (i = 0; i < GPE0_REG_MAX; i++) |
Michael Niewöhner | 820b9c4 | 2021-09-30 21:03:07 +0200 | [diff] [blame] | 208 | gpe0_sts[i] = ps->gpe0_sts[i] & gpe0_en[i]; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 209 | |
| 210 | return GPE0_REG_MAX; |
| 211 | } |
| 212 | |
Marc Jones | a81703c | 2020-12-18 10:44:47 -0700 | [diff] [blame] | 213 | int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 214 | { |
| 215 | u32 m; |
| 216 | u32 power; |
| 217 | |
| 218 | /* |
| 219 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 220 | * |
| 221 | * Power = (ratio / p1_ratio) * m * tdp |
| 222 | */ |
| 223 | |
| 224 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 225 | m = (m * m) / 1000; |
| 226 | |
| 227 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 228 | power *= (m / 100) * (tdp / 1000); |
| 229 | power /= 1000; |
| 230 | |
| 231 | return power; |
| 232 | } |
| 233 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 234 | static void generate_c_state_entries(void) |
| 235 | { |
Angel Pons | e9f10ff | 2021-10-17 13:28:23 +0200 | [diff] [blame] | 236 | const acpi_cstate_t *c_state_map; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 237 | size_t entries; |
| 238 | |
| 239 | c_state_map = soc_get_cstate_map(&entries); |
| 240 | |
| 241 | /* Generate C-state tables */ |
| 242 | acpigen_write_CST_package(c_state_map, entries); |
| 243 | } |
| 244 | |
| 245 | void generate_p_state_entries(int core, int cores_per_package) |
| 246 | { |
| 247 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 248 | int coord_type, power_max, num_entries; |
| 249 | int ratio, power, clock, clock_max; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 250 | bool turbo; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 251 | |
| 252 | coord_type = cpu_get_coord_type(); |
| 253 | ratio_min = cpu_get_min_ratio(); |
| 254 | ratio_max = cpu_get_max_ratio(); |
| 255 | clock_max = (ratio_max * cpu_get_bus_clock()) / KHz; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 256 | turbo = (get_turbo_state() == TURBO_ENABLED); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 257 | |
| 258 | /* Calculate CPU TDP in mW */ |
| 259 | power_max = cpu_get_power_max(); |
| 260 | |
| 261 | /* Write _PCT indicating use of FFixedHW */ |
| 262 | acpigen_write_empty_PCT(); |
| 263 | |
| 264 | /* Write _PPC with no limit on supported P-state */ |
| 265 | acpigen_write_PPC_NVS(); |
| 266 | /* Write PSD indicating configured coordination type */ |
| 267 | acpigen_write_PSD_package(core, 1, coord_type); |
| 268 | |
| 269 | /* Add P-state entries in _PSS table */ |
| 270 | acpigen_write_name("_PSS"); |
| 271 | |
| 272 | /* Determine ratio points */ |
| 273 | ratio_step = PSS_RATIO_STEP; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 274 | do { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 275 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 276 | if (((ratio_max - ratio_min) % ratio_step) > 0) |
| 277 | num_entries += 1; |
| 278 | if (turbo) |
| 279 | num_entries += 1; |
| 280 | if (num_entries > PSS_MAX_ENTRIES) |
| 281 | ratio_step += 1; |
| 282 | } while (num_entries > PSS_MAX_ENTRIES); |
| 283 | |
| 284 | /* _PSS package count depends on Turbo */ |
| 285 | acpigen_write_package(num_entries); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 286 | |
| 287 | /* P[T] is Turbo state if enabled */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 288 | if (turbo) { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 289 | ratio_turbo = cpu_get_max_turbo_ratio(); |
| 290 | |
| 291 | /* Add entry for Turbo ratio */ |
| 292 | acpigen_write_PSS_package(clock_max + 1, /* MHz */ |
| 293 | power_max, /* mW */ |
| 294 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 295 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 296 | ratio_turbo << 8, /* control */ |
| 297 | ratio_turbo << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 298 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | /* First regular entry is max non-turbo ratio */ |
| 302 | acpigen_write_PSS_package(clock_max, /* MHz */ |
| 303 | power_max, /* mW */ |
| 304 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 305 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 306 | ratio_max << 8, /* control */ |
| 307 | ratio_max << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 308 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 309 | |
| 310 | /* Generate the remaining entries */ |
| 311 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 312 | ratio >= ratio_min; ratio -= ratio_step) { |
| 313 | |
| 314 | /* Calculate power at this ratio */ |
Marc Jones | a81703c | 2020-12-18 10:44:47 -0700 | [diff] [blame] | 315 | power = common_calculate_power_ratio(power_max, ratio_max, ratio); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 316 | clock = (ratio * cpu_get_bus_clock()) / KHz; |
| 317 | |
| 318 | acpigen_write_PSS_package(clock, /* MHz */ |
| 319 | power, /* mW */ |
| 320 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 321 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 322 | ratio << 8, /* control */ |
| 323 | ratio << 8); /* status */ |
| 324 | } |
| 325 | /* Fix package length */ |
| 326 | acpigen_pop_len(); |
| 327 | } |
| 328 | |
Julien Viard de Galbert | 595202c | 2018-03-29 14:01:01 +0200 | [diff] [blame] | 329 | __attribute__ ((weak)) acpi_tstate_t *soc_get_tss_table(int *entries) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 330 | { |
| 331 | *entries = 0; |
| 332 | return NULL; |
| 333 | } |
| 334 | |
| 335 | void generate_t_state_entries(int core, int cores_per_package) |
| 336 | { |
| 337 | acpi_tstate_t *soc_tss_table; |
| 338 | int entries; |
| 339 | |
| 340 | soc_tss_table = soc_get_tss_table(&entries); |
| 341 | if (entries == 0) |
| 342 | return; |
| 343 | |
| 344 | /* Indicate SW_ALL coordination for T-states */ |
| 345 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
| 346 | |
| 347 | /* Indicate FixedHW so OS will use MSR */ |
| 348 | acpigen_write_empty_PTC(); |
| 349 | |
| 350 | /* Set NVS controlled T-state limit */ |
| 351 | acpigen_write_TPC("\\TLVL"); |
| 352 | |
| 353 | /* Write TSS table for MSR access */ |
| 354 | acpigen_write_TSS_package(entries, soc_tss_table); |
| 355 | } |
| 356 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 357 | static void generate_cppc_entries(int core_id) |
| 358 | { |
Sridhar Siricilla | 1173612 | 2021-11-15 17:12:49 +0530 | [diff] [blame] | 359 | u32 version = CPPC_VERSION_2; |
| 360 | |
| 361 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) |
| 362 | version = CPPC_VERSION_3; |
| 363 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 364 | if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && |
| 365 | cpuid_eax(6) & CPUID_6_EAX_ISST)) |
| 366 | return; |
| 367 | |
| 368 | /* Generate GCPC package in first logical core */ |
| 369 | if (core_id == 0) { |
| 370 | struct cppc_config cppc_config; |
Sridhar Siricilla | 1173612 | 2021-11-15 17:12:49 +0530 | [diff] [blame] | 371 | cpu_init_cppc_config(&cppc_config, version); |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 372 | acpigen_write_CPPC_package(&cppc_config); |
| 373 | } |
| 374 | |
| 375 | /* Write _CPC entry for each logical core */ |
Sridhar Siricilla | 1173612 | 2021-11-15 17:12:49 +0530 | [diff] [blame] | 376 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) |
| 377 | acpigen_write_CPPC_hybrid_method(core_id); |
| 378 | else |
| 379 | acpigen_write_CPPC_method(); |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 380 | } |
| 381 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 382 | __weak void soc_power_states_generation(int core_id, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 383 | int cores_per_package) |
| 384 | { |
| 385 | } |
| 386 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 387 | void generate_cpu_entries(const struct device *device) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 388 | { |
Michael Niewöhner | 2353cd9 | 2021-10-04 16:59:49 +0200 | [diff] [blame] | 389 | int core_id, cpu_id; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 390 | int totalcores = dev_count_cpu(); |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 391 | unsigned int num_virt; |
| 392 | unsigned int num_phys; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 393 | |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 394 | cpu_read_topology(&num_phys, &num_virt); |
| 395 | |
| 396 | int numcpus = totalcores / num_virt; |
| 397 | |
| 398 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d/%d physical/logical core(s) each.\n", |
| 399 | numcpus, num_phys, num_virt); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 400 | |
| 401 | for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 402 | for (core_id = 0; core_id < num_virt; core_id++) { |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 403 | /* Generate processor \_SB.CPUx */ |
Patrick Rudolph | 0f0b619 | 2023-02-28 07:28:56 +0100 | [diff] [blame] | 404 | acpigen_write_processor_device(cpu_id * num_virt + core_id); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 405 | |
| 406 | /* Generate C-state tables */ |
| 407 | generate_c_state_entries(); |
| 408 | |
Michael Niewöhner | ed21df6 | 2020-09-19 00:08:45 +0200 | [diff] [blame] | 409 | generate_cppc_entries(core_id); |
| 410 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 411 | /* Soc specific power states generation */ |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 412 | soc_power_states_generation(core_id, num_virt); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 413 | |
Kyösti Mälkki | c77b607 | 2023-04-12 19:18:32 +0300 | [diff] [blame] | 414 | acpigen_write_processor_device_end(); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 415 | } |
| 416 | } |
Arthur Heymans | 0ac555e | 2018-11-28 12:25:54 +0100 | [diff] [blame] | 417 | /* PPKG is usually used for thermal management |
| 418 | of the first and only package. */ |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 419 | acpigen_write_processor_package("PPKG", 0, num_virt); |
Arthur Heymans | 0ac555e | 2018-11-28 12:25:54 +0100 | [diff] [blame] | 420 | |
| 421 | /* Add a method to notify processor nodes */ |
Patrick Rudolph | 7a66ffb | 2020-12-17 14:42:29 +0100 | [diff] [blame] | 422 | acpigen_write_processor_cnot(num_virt); |
Michael Niewöhner | b48caad | 2021-10-17 15:36:45 +0200 | [diff] [blame] | 423 | |
| 424 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) |
| 425 | sgx_fill_ssdt(); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 426 | } |