blob: 2948faf9b9ef9b60f776bdda3d66a5d5e0bab440 [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Elyes HAOUASa1e22b82019-03-18 22:49:36 +01002
Furquan Shaikh76cedd22020-05-02 10:24:23 -07003#include <acpi/acpigen.h>
Michael Niewöhnered21df62020-09-19 00:08:45 +02004#include <arch/cpu.h>
Shaunak Sahabd427802017-07-18 00:19:33 -07005#include <arch/ioapic.h>
6#include <arch/smp/mpspec.h>
7#include <bootstate.h>
8#include <cbmem.h>
Patrick Rudolphf677d172018-10-01 19:17:11 +02009#include <cf9_reset.h>
Kyösti Mälkki5daa1d32020-06-14 12:01:58 +030010#include <acpi/acpi_gnvs.h>
Elyes HAOUAS20eaef02019-03-29 17:45:28 +010011#include <console/console.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070012#include <cpu/intel/turbo.h>
Michael Niewöhnered21df62020-09-19 00:08:45 +020013#include <cpu/intel/common/common.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070014#include <cpu/x86/smm.h>
15#include <intelblocks/acpi.h>
Marc Jones1403b912020-12-02 14:35:27 -070016#include <intelblocks/lpc_lib.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070017#include <intelblocks/msr.h>
18#include <intelblocks/pmclib.h>
Duncan Laurie93bbd412017-11-11 20:03:29 -080019#include <intelblocks/uart.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070020#include <soc/gpio.h>
21#include <soc/iomap.h>
22#include <soc/nvs.h>
23#include <soc/pm.h>
Elyes HAOUASa1e22b82019-03-18 22:49:36 +010024#include <string.h>
Shaunak Sahabd427802017-07-18 00:19:33 -070025
Michael Niewöhnered21df62020-09-19 00:08:45 +020026#define CPUID_6_EAX_ISST (1 << 7)
27
Julien Viard de Galbertcf2b72f2018-04-05 11:24:45 +020028__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current)
Shaunak Sahabd427802017-07-18 00:19:33 -070029{
30 /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
31 current += acpi_create_mcfg_mmconfig((void *)current,
32 CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
Duncan Lauriefd50b7c2018-03-02 14:47:11 -080033 (CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
Shaunak Sahabd427802017-07-18 00:19:33 -070034 return current;
35}
36
37static int acpi_sci_irq(void)
38{
39 int sci_irq = 9;
40 uint32_t scis;
41
42 scis = soc_read_sci_irq_select();
43 scis &= SCI_IRQ_SEL;
44 scis >>= SCI_IRQ_ADJUST;
45
46 /* Determine how SCI is routed. */
47 switch (scis) {
48 case SCIS_IRQ9:
49 case SCIS_IRQ10:
50 case SCIS_IRQ11:
51 sci_irq = scis - SCIS_IRQ9 + 9;
52 break;
53 case SCIS_IRQ20:
54 case SCIS_IRQ21:
55 case SCIS_IRQ22:
56 case SCIS_IRQ23:
57 sci_irq = scis - SCIS_IRQ20 + 20;
58 break;
59 default:
60 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
61 sci_irq = 9;
62 break;
63 }
64
65 printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
66 return sci_irq;
67}
68
69static unsigned long acpi_madt_irq_overrides(unsigned long current)
70{
71 int sci = acpi_sci_irq();
72 uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
73
74 /* INT_SRC_OVR */
75 current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
76
77 flags |= soc_madt_sci_irq_polarity(sci);
78
79 /* SCI */
80 current +=
81 acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
82
Michael Niewöhner14512f92020-11-23 15:53:28 +010083 /* NMI */
84 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
85
Shaunak Sahabd427802017-07-18 00:19:33 -070086 return current;
87}
88
89unsigned long acpi_fill_madt(unsigned long current)
90{
91 /* Local APICs */
92 current = acpi_create_madt_lapics(current);
93
94 /* IOAPIC */
95 current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0);
96
97 return acpi_madt_irq_overrides(current);
98}
99
Shaunak Sahabd427802017-07-18 00:19:33 -0700100void acpi_fill_fadt(acpi_fadt_t *fadt)
101{
102 const uint16_t pmbase = ACPI_BASE_ADDRESS;
103
Marc Jonesf9ea7ed2018-08-22 18:59:26 -0600104 fadt->header.revision = get_acpi_table_revision(FADT);
Shaunak Sahabd427802017-07-18 00:19:33 -0700105
106 fadt->sci_int = acpi_sci_irq();
Kyösti Mälkkic328a682019-11-23 07:23:40 +0200107
Kyösti Mälkki0a9e72e2019-08-11 01:22:28 +0300108 if (permanent_smi_handler()) {
Kyösti Mälkkic328a682019-11-23 07:23:40 +0200109 fadt->smi_cmd = APM_CNT;
110 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
111 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
112 }
Shaunak Sahabd427802017-07-18 00:19:33 -0700113
114 fadt->pm1a_evt_blk = pmbase + PM1_STS;
Shaunak Sahabd427802017-07-18 00:19:33 -0700115 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
Shaunak Sahabd427802017-07-18 00:19:33 -0700116
117 fadt->gpe0_blk = pmbase + GPE0_STS(0);
118
119 fadt->pm1_evt_len = 4;
120 fadt->pm1_cnt_len = 2;
121
122 /* GPE0 STS/EN pairs each 32 bits wide. */
123 fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
124
Shaunak Sahabd427802017-07-18 00:19:33 -0700125 fadt->duty_offset = 1;
126 fadt->day_alrm = 0xd;
127
Angel Ponsa208c6c2020-07-13 00:02:34 +0200128 fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
129 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
Angel Pons79572e42020-07-13 00:17:43 +0200130 ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
131 ACPI_FADT_PLATFORM_CLOCK;
Shaunak Sahabd427802017-07-18 00:19:33 -0700132
Elyes HAOUAS04071f42020-07-20 17:05:24 +0200133 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
Shaunak Sahabd427802017-07-18 00:19:33 -0700134 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
135 fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
Angel Pons12a4d052020-07-14 01:31:27 +0200136 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100137
Elyes HAOUAS04071f42020-07-20 17:05:24 +0200138 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
Shaunak Sahabd427802017-07-18 00:19:33 -0700139 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
140 fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100141 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
Shaunak Sahabd427802017-07-18 00:19:33 -0700142
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100143 /*
144 * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
145 * The bit_width field intentionally overflows here.
146 * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
147 * seems to work fine on Linux 5.0 and Windows 10.
148 */
149 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
150 fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
151 fadt->x_gpe0_blk.bit_offset = 0;
Angel Ponsa23aff32020-06-21 20:47:54 +0200152 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
Patrick Rudolphc02bda02020-02-28 10:19:41 +0100153 fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
154 fadt->x_gpe0_blk.addrh = 0;
Shaunak Sahabd427802017-07-18 00:19:33 -0700155}
156
Furquan Shaikh0f007d82020-04-24 06:41:18 -0700157unsigned long southbridge_write_acpi_tables(const struct device *device,
Shaunak Sahabd427802017-07-18 00:19:33 -0700158 unsigned long current,
159 struct acpi_rsdp *rsdp)
160{
Duncan Laurie93bbd412017-11-11 20:03:29 -0800161 current = acpi_write_dbg2_pci_uart(rsdp, current,
Subrata Banikafa07f72018-05-24 12:21:06 +0530162 uart_get_device(),
Duncan Laurie93bbd412017-11-11 20:03:29 -0800163 ACPI_ACCESS_SIZE_DWORD_ACCESS);
Shaunak Sahabd427802017-07-18 00:19:33 -0700164 return acpi_write_hpet(device, current, rsdp);
165}
166
Aaron Durbin64031672018-04-21 14:45:32 -0600167__weak
Shaunak Sahabd427802017-07-18 00:19:33 -0700168uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
169 const struct chipset_power_state *ps)
170{
171 return generic_pm1_en;
172}
173
Julius Wernercd49cce2019-03-05 16:53:33 -0800174#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
Shaunak Sahabd427802017-07-18 00:19:33 -0700175/*
176 * Save wake source information for calculating ACPI _SWS values
177 *
178 * @pm1: PM1_STS register with only enabled events set
179 * @gpe0: GPE0_STS registers with only enabled events set
180 *
181 * return the number of registers in the gpe0 array or -1 if nothing
182 * is provided by this function.
183 */
184
185static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0)
186{
187 struct chipset_power_state *ps;
188 static uint32_t gpe0_sts[GPE0_REG_MAX];
189 uint32_t pm1_en;
190 int i;
191
192 ps = cbmem_find(CBMEM_ID_POWER_STATE);
193 if (ps == NULL)
194 return -1;
195
196 /*
197 * PM1_EN to check the basic wake events which can happen through
198 * powerbtn or any other wake source like lidopen, key board press etc.
199 */
200 pm1_en = ps->pm1_en;
201
202 pm1_en = acpi_fill_soc_wake(pm1_en, ps);
203
204 *pm1 = ps->pm1_sts & pm1_en;
205
206 /* Mask off GPE0 status bits that are not enabled */
207 *gpe0 = &gpe0_sts[0];
208 for (i = 0; i < GPE0_REG_MAX; i++)
209 gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
210
211 return GPE0_REG_MAX;
212}
Julien Viard de Galbertcf2b72f2018-04-05 11:24:45 +0200213#endif
Shaunak Sahabd427802017-07-18 00:19:33 -0700214
Kyösti Mälkki0c1dd9c2020-06-17 23:37:49 +0300215__weak void acpi_create_gnvs(struct global_nvs *gnvs)
Shaunak Sahabd427802017-07-18 00:19:33 -0700216{
217}
218
Furquan Shaikh338fd9a2020-04-24 22:57:05 -0700219void southbridge_inject_dsdt(const struct device *device)
Shaunak Sahabd427802017-07-18 00:19:33 -0700220{
Kyösti Mälkki0c1dd9c2020-06-17 23:37:49 +0300221 struct global_nvs *gnvs;
Shaunak Sahabd427802017-07-18 00:19:33 -0700222
223 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
224 if (!gnvs) {
225 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
226 if (gnvs)
227 memset(gnvs, 0, sizeof(*gnvs));
228 }
229
230 if (gnvs) {
231 acpi_create_gnvs(gnvs);
Shaunak Sahabd427802017-07-18 00:19:33 -0700232 /* And tell SMI about it */
Kyösti Mälkkic3c55212020-06-17 10:34:26 +0300233 apm_control(APM_CNT_GNVS_UPDATE);
Shaunak Sahabd427802017-07-18 00:19:33 -0700234
235 /* Add it to DSDT. */
236 acpigen_write_scope("\\");
237 acpigen_write_name_dword("NVSA", (uintptr_t) gnvs);
238 acpigen_pop_len();
239 }
240}
241
242static int calculate_power(int tdp, int p1_ratio, int ratio)
243{
244 u32 m;
245 u32 power;
246
247 /*
248 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
249 *
250 * Power = (ratio / p1_ratio) * m * tdp
251 */
252
253 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
254 m = (m * m) / 1000;
255
256 power = ((ratio * 100000 / p1_ratio) / 100);
257 power *= (m / 100) * (tdp / 1000);
258 power /= 1000;
259
260 return power;
261}
262
263static int get_cores_per_package(void)
264{
265 struct cpuinfo_x86 c;
266 struct cpuid_result result;
267 int cores = 1;
268
269 get_fms(&c, cpuid_eax(1));
270 if (c.x86 != 6)
271 return 1;
272
273 result = cpuid_ext(0xb, 1);
274 cores = result.ebx & 0xff;
275
276 return cores;
277}
278
279static void generate_c_state_entries(void)
280{
281 acpi_cstate_t *c_state_map;
282 size_t entries;
283
284 c_state_map = soc_get_cstate_map(&entries);
285
286 /* Generate C-state tables */
287 acpigen_write_CST_package(c_state_map, entries);
288}
289
290void generate_p_state_entries(int core, int cores_per_package)
291{
292 int ratio_min, ratio_max, ratio_turbo, ratio_step;
293 int coord_type, power_max, num_entries;
294 int ratio, power, clock, clock_max;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100295 bool turbo;
Shaunak Sahabd427802017-07-18 00:19:33 -0700296
297 coord_type = cpu_get_coord_type();
298 ratio_min = cpu_get_min_ratio();
299 ratio_max = cpu_get_max_ratio();
300 clock_max = (ratio_max * cpu_get_bus_clock()) / KHz;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100301 turbo = (get_turbo_state() == TURBO_ENABLED);
Shaunak Sahabd427802017-07-18 00:19:33 -0700302
303 /* Calculate CPU TDP in mW */
304 power_max = cpu_get_power_max();
305
306 /* Write _PCT indicating use of FFixedHW */
307 acpigen_write_empty_PCT();
308
309 /* Write _PPC with no limit on supported P-state */
310 acpigen_write_PPC_NVS();
311 /* Write PSD indicating configured coordination type */
312 acpigen_write_PSD_package(core, 1, coord_type);
313
314 /* Add P-state entries in _PSS table */
315 acpigen_write_name("_PSS");
316
317 /* Determine ratio points */
318 ratio_step = PSS_RATIO_STEP;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100319 do {
Shaunak Sahabd427802017-07-18 00:19:33 -0700320 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100321 if (((ratio_max - ratio_min) % ratio_step) > 0)
322 num_entries += 1;
323 if (turbo)
324 num_entries += 1;
325 if (num_entries > PSS_MAX_ENTRIES)
326 ratio_step += 1;
327 } while (num_entries > PSS_MAX_ENTRIES);
328
329 /* _PSS package count depends on Turbo */
330 acpigen_write_package(num_entries);
Shaunak Sahabd427802017-07-18 00:19:33 -0700331
332 /* P[T] is Turbo state if enabled */
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100333 if (turbo) {
Shaunak Sahabd427802017-07-18 00:19:33 -0700334 ratio_turbo = cpu_get_max_turbo_ratio();
335
336 /* Add entry for Turbo ratio */
337 acpigen_write_PSS_package(clock_max + 1, /* MHz */
338 power_max, /* mW */
339 PSS_LATENCY_TRANSITION,/* lat1 */
340 PSS_LATENCY_BUSMASTER,/* lat2 */
341 ratio_turbo << 8, /* control */
342 ratio_turbo << 8); /* status */
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100343 num_entries -= 1;
Shaunak Sahabd427802017-07-18 00:19:33 -0700344 }
345
346 /* First regular entry is max non-turbo ratio */
347 acpigen_write_PSS_package(clock_max, /* MHz */
348 power_max, /* mW */
349 PSS_LATENCY_TRANSITION,/* lat1 */
350 PSS_LATENCY_BUSMASTER,/* lat2 */
351 ratio_max << 8, /* control */
352 ratio_max << 8); /* status */
Julien Viard de Galbertc2540a92018-11-06 09:28:03 +0100353 num_entries -= 1;
Shaunak Sahabd427802017-07-18 00:19:33 -0700354
355 /* Generate the remaining entries */
356 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
357 ratio >= ratio_min; ratio -= ratio_step) {
358
359 /* Calculate power at this ratio */
360 power = calculate_power(power_max, ratio_max, ratio);
361 clock = (ratio * cpu_get_bus_clock()) / KHz;
362
363 acpigen_write_PSS_package(clock, /* MHz */
364 power, /* mW */
365 PSS_LATENCY_TRANSITION,/* lat1 */
366 PSS_LATENCY_BUSMASTER,/* lat2 */
367 ratio << 8, /* control */
368 ratio << 8); /* status */
369 }
370 /* Fix package length */
371 acpigen_pop_len();
372}
373
Julien Viard de Galbert595202c2018-03-29 14:01:01 +0200374__attribute__ ((weak)) acpi_tstate_t *soc_get_tss_table(int *entries)
Shaunak Sahabd427802017-07-18 00:19:33 -0700375{
376 *entries = 0;
377 return NULL;
378}
379
380void generate_t_state_entries(int core, int cores_per_package)
381{
382 acpi_tstate_t *soc_tss_table;
383 int entries;
384
385 soc_tss_table = soc_get_tss_table(&entries);
386 if (entries == 0)
387 return;
388
389 /* Indicate SW_ALL coordination for T-states */
390 acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
391
392 /* Indicate FixedHW so OS will use MSR */
393 acpigen_write_empty_PTC();
394
395 /* Set NVS controlled T-state limit */
396 acpigen_write_TPC("\\TLVL");
397
398 /* Write TSS table for MSR access */
399 acpigen_write_TSS_package(entries, soc_tss_table);
400}
401
Michael Niewöhnered21df62020-09-19 00:08:45 +0200402static void generate_cppc_entries(int core_id)
403{
404 if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) &&
405 cpuid_eax(6) & CPUID_6_EAX_ISST))
406 return;
407
408 /* Generate GCPC package in first logical core */
409 if (core_id == 0) {
410 struct cppc_config cppc_config;
411 cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2);
412 acpigen_write_CPPC_package(&cppc_config);
413 }
414
415 /* Write _CPC entry for each logical core */
416 acpigen_write_CPPC_method();
417}
418
Aaron Durbin64031672018-04-21 14:45:32 -0600419__weak void soc_power_states_generation(int core_id,
Shaunak Sahabd427802017-07-18 00:19:33 -0700420 int cores_per_package)
421{
422}
423
Furquan Shaikh7536a392020-04-24 21:59:21 -0700424void generate_cpu_entries(const struct device *device)
Shaunak Sahabd427802017-07-18 00:19:33 -0700425{
426 int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
427 int plen = 6;
428 int totalcores = dev_count_cpu();
429 int cores_per_package = get_cores_per_package();
430 int numcpus = totalcores / cores_per_package;
431
432 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
433 numcpus, cores_per_package);
434
435 for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
436 for (core_id = 0; core_id < cores_per_package; core_id++) {
437 if (core_id > 0) {
438 pcontrol_blk = 0;
439 plen = 0;
440 }
441
Christian Walterbe3979c2019-12-18 15:07:59 +0100442 /* Generate processor \_SB.CPUx */
Shaunak Sahabd427802017-07-18 00:19:33 -0700443 acpigen_write_processor((cpu_id) * cores_per_package +
444 core_id, pcontrol_blk, plen);
445
446 /* Generate C-state tables */
447 generate_c_state_entries();
448
Michael Niewöhnered21df62020-09-19 00:08:45 +0200449 generate_cppc_entries(core_id);
450
Shaunak Sahabd427802017-07-18 00:19:33 -0700451 /* Soc specific power states generation */
452 soc_power_states_generation(core_id, cores_per_package);
453
454 acpigen_pop_len();
455 }
456 }
Arthur Heymans0ac555e2018-11-28 12:25:54 +0100457 /* PPKG is usually used for thermal management
458 of the first and only package. */
459 acpigen_write_processor_package("PPKG", 0, cores_per_package);
460
461 /* Add a method to notify processor nodes */
462 acpigen_write_processor_cnot(cores_per_package);
Shaunak Sahabd427802017-07-18 00:19:33 -0700463}
464
Julius Wernercd49cce2019-03-05 16:53:33 -0800465#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
Shaunak Sahabd427802017-07-18 00:19:33 -0700466/* Save wake source data for ACPI _SWS methods in NVS */
467static void acpi_save_wake_source(void *unused)
468{
Kyösti Mälkki0c1dd9c2020-06-17 23:37:49 +0300469 struct global_nvs *gnvs = acpi_get_gnvs();
Shaunak Sahabd427802017-07-18 00:19:33 -0700470 uint32_t pm1, *gpe0;
471 int gpe_reg, gpe_reg_count;
472 int reg_size = sizeof(uint32_t) * 8;
473
474 if (!gnvs)
475 return;
476
477 gnvs->pm1i = -1;
478 gnvs->gpei = -1;
479
480 gpe_reg_count = acpi_fill_wake(&pm1, &gpe0);
481 if (gpe_reg_count < 0)
482 return;
483
484 /* Scan for first set bit in PM1 */
485 for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) {
486 if (pm1 & 1)
487 break;
488 pm1 >>= 1;
489 }
490
491 /* If unable to determine then return -1 */
492 if (gnvs->pm1i >= 16)
493 gnvs->pm1i = -1;
494
495 /* Scan for first set bit in GPE registers */
496 for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) {
497 uint32_t gpe = gpe0[gpe_reg];
498 int start = gpe_reg * reg_size;
499 int end = start + reg_size;
500
501 if (gpe == 0) {
502 if (!gnvs->gpei)
503 gnvs->gpei = end;
504 continue;
505 }
506
507 for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
508 if (gpe & 1)
509 break;
510 gpe >>= 1;
511 }
512 }
513
514 /* If unable to determine then return -1 */
515 if (gnvs->gpei >= gpe_reg_count * reg_size)
516 gnvs->gpei = -1;
517
518 printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
519 (long long)gnvs->pm1i, (long long)gnvs->gpei);
520}
521
522BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL);
523
524#endif