Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame^] | 16 | |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 17 | #include <arch/acpigen.h> |
| 18 | #include <arch/ioapic.h> |
| 19 | #include <arch/smp/mpspec.h> |
| 20 | #include <bootstate.h> |
| 21 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 22 | #include <cf9_reset.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 23 | #include <cpu/intel/turbo.h> |
| 24 | #include <cpu/x86/msr.h> |
| 25 | #include <cpu/x86/smm.h> |
| 26 | #include <intelblocks/acpi.h> |
| 27 | #include <intelblocks/msr.h> |
| 28 | #include <intelblocks/pmclib.h> |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 29 | #include <intelblocks/uart.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 30 | #include <soc/gpio.h> |
| 31 | #include <soc/iomap.h> |
| 32 | #include <soc/nvs.h> |
| 33 | #include <soc/pm.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame^] | 34 | #include <string.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 35 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame] | 36 | __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 37 | { |
| 38 | /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ |
| 39 | current += acpi_create_mcfg_mmconfig((void *)current, |
| 40 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, |
Duncan Laurie | fd50b7c | 2018-03-02 14:47:11 -0800 | [diff] [blame] | 41 | (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 42 | return current; |
| 43 | } |
| 44 | |
| 45 | static int acpi_sci_irq(void) |
| 46 | { |
| 47 | int sci_irq = 9; |
| 48 | uint32_t scis; |
| 49 | |
| 50 | scis = soc_read_sci_irq_select(); |
| 51 | scis &= SCI_IRQ_SEL; |
| 52 | scis >>= SCI_IRQ_ADJUST; |
| 53 | |
| 54 | /* Determine how SCI is routed. */ |
| 55 | switch (scis) { |
| 56 | case SCIS_IRQ9: |
| 57 | case SCIS_IRQ10: |
| 58 | case SCIS_IRQ11: |
| 59 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 60 | break; |
| 61 | case SCIS_IRQ20: |
| 62 | case SCIS_IRQ21: |
| 63 | case SCIS_IRQ22: |
| 64 | case SCIS_IRQ23: |
| 65 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 66 | break; |
| 67 | default: |
| 68 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); |
| 69 | sci_irq = 9; |
| 70 | break; |
| 71 | } |
| 72 | |
| 73 | printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); |
| 74 | return sci_irq; |
| 75 | } |
| 76 | |
| 77 | static unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 78 | { |
| 79 | int sci = acpi_sci_irq(); |
| 80 | uint16_t flags = MP_IRQ_TRIGGER_LEVEL; |
| 81 | |
| 82 | /* INT_SRC_OVR */ |
| 83 | current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); |
| 84 | |
| 85 | flags |= soc_madt_sci_irq_polarity(sci); |
| 86 | |
| 87 | /* SCI */ |
| 88 | current += |
| 89 | acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); |
| 90 | |
| 91 | return current; |
| 92 | } |
| 93 | |
| 94 | unsigned long acpi_fill_madt(unsigned long current) |
| 95 | { |
| 96 | /* Local APICs */ |
| 97 | current = acpi_create_madt_lapics(current); |
| 98 | |
| 99 | /* IOAPIC */ |
| 100 | current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); |
| 101 | |
| 102 | return acpi_madt_irq_overrides(current); |
| 103 | } |
| 104 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 105 | __weak void soc_fill_fadt(acpi_fadt_t *fadt) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 106 | { |
| 107 | } |
| 108 | |
| 109 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 110 | { |
| 111 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 112 | |
| 113 | /* Use ACPI 3.0 revision. */ |
Marc Jones | f9ea7ed | 2018-08-22 18:59:26 -0600 | [diff] [blame] | 114 | fadt->header.revision = get_acpi_table_revision(FADT); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 115 | |
| 116 | fadt->sci_int = acpi_sci_irq(); |
| 117 | fadt->smi_cmd = APM_CNT; |
| 118 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 119 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 120 | fadt->s4bios_req = 0x0; |
| 121 | fadt->pstate_cnt = 0; |
| 122 | |
| 123 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 124 | fadt->pm1b_evt_blk = 0x0; |
| 125 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 126 | fadt->pm1b_cnt_blk = 0x0; |
| 127 | |
| 128 | fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| 129 | |
| 130 | fadt->pm1_evt_len = 4; |
| 131 | fadt->pm1_cnt_len = 2; |
| 132 | |
| 133 | /* GPE0 STS/EN pairs each 32 bits wide. */ |
| 134 | fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); |
| 135 | |
| 136 | fadt->flush_size = 0x400; /* twice of cache size */ |
| 137 | fadt->flush_stride = 0x10; /* Cache line width */ |
| 138 | fadt->duty_offset = 1; |
| 139 | fadt->day_alrm = 0xd; |
| 140 | |
| 141 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 142 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 143 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | |
| 144 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 145 | |
| 146 | fadt->reset_reg.space_id = 1; |
| 147 | fadt->reset_reg.bit_width = 8; |
| 148 | fadt->reset_reg.addrl = RST_CNT; |
| 149 | fadt->reset_value = RST_CPU | SYS_RST; |
| 150 | |
| 151 | fadt->x_pm1a_evt_blk.space_id = 1; |
| 152 | fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
| 153 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| 154 | |
| 155 | fadt->x_pm1b_evt_blk.space_id = 1; |
| 156 | |
| 157 | fadt->x_pm1a_cnt_blk.space_id = 1; |
| 158 | fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
| 159 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| 160 | |
| 161 | fadt->x_pm1b_cnt_blk.space_id = 1; |
| 162 | |
| 163 | fadt->x_gpe1_blk.space_id = 1; |
| 164 | |
| 165 | soc_fill_fadt(fadt); |
| 166 | } |
| 167 | |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 168 | unsigned long southbridge_write_acpi_tables(struct device *device, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 169 | unsigned long current, |
| 170 | struct acpi_rsdp *rsdp) |
| 171 | { |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 172 | current = acpi_write_dbg2_pci_uart(rsdp, current, |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 173 | uart_get_device(), |
Duncan Laurie | 93bbd41 | 2017-11-11 20:03:29 -0800 | [diff] [blame] | 174 | ACPI_ACCESS_SIZE_DWORD_ACCESS); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 175 | return acpi_write_hpet(device, current, rsdp); |
| 176 | } |
| 177 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 178 | __weak |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 179 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 180 | const struct chipset_power_state *ps) |
| 181 | { |
| 182 | return generic_pm1_en; |
| 183 | } |
| 184 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 185 | #if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 186 | /* |
| 187 | * Save wake source information for calculating ACPI _SWS values |
| 188 | * |
| 189 | * @pm1: PM1_STS register with only enabled events set |
| 190 | * @gpe0: GPE0_STS registers with only enabled events set |
| 191 | * |
| 192 | * return the number of registers in the gpe0 array or -1 if nothing |
| 193 | * is provided by this function. |
| 194 | */ |
| 195 | |
| 196 | static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0) |
| 197 | { |
| 198 | struct chipset_power_state *ps; |
| 199 | static uint32_t gpe0_sts[GPE0_REG_MAX]; |
| 200 | uint32_t pm1_en; |
| 201 | int i; |
| 202 | |
| 203 | ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 204 | if (ps == NULL) |
| 205 | return -1; |
| 206 | |
| 207 | /* |
| 208 | * PM1_EN to check the basic wake events which can happen through |
| 209 | * powerbtn or any other wake source like lidopen, key board press etc. |
| 210 | */ |
| 211 | pm1_en = ps->pm1_en; |
| 212 | |
| 213 | pm1_en = acpi_fill_soc_wake(pm1_en, ps); |
| 214 | |
| 215 | *pm1 = ps->pm1_sts & pm1_en; |
| 216 | |
| 217 | /* Mask off GPE0 status bits that are not enabled */ |
| 218 | *gpe0 = &gpe0_sts[0]; |
| 219 | for (i = 0; i < GPE0_REG_MAX; i++) |
| 220 | gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; |
| 221 | |
| 222 | return GPE0_REG_MAX; |
| 223 | } |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame] | 224 | #endif |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 225 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 226 | __weak void acpi_create_gnvs(struct global_nvs_t *gnvs) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 227 | { |
| 228 | } |
| 229 | |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 230 | void southbridge_inject_dsdt(struct device *device) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 231 | { |
| 232 | struct global_nvs_t *gnvs; |
| 233 | |
| 234 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 235 | if (!gnvs) { |
| 236 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
| 237 | if (gnvs) |
| 238 | memset(gnvs, 0, sizeof(*gnvs)); |
| 239 | } |
| 240 | |
| 241 | if (gnvs) { |
| 242 | acpi_create_gnvs(gnvs); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 243 | /* And tell SMI about it */ |
| 244 | smm_setup_structures(gnvs, NULL, NULL); |
| 245 | |
| 246 | /* Add it to DSDT. */ |
| 247 | acpigen_write_scope("\\"); |
| 248 | acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); |
| 249 | acpigen_pop_len(); |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 254 | { |
| 255 | u32 m; |
| 256 | u32 power; |
| 257 | |
| 258 | /* |
| 259 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 260 | * |
| 261 | * Power = (ratio / p1_ratio) * m * tdp |
| 262 | */ |
| 263 | |
| 264 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 265 | m = (m * m) / 1000; |
| 266 | |
| 267 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 268 | power *= (m / 100) * (tdp / 1000); |
| 269 | power /= 1000; |
| 270 | |
| 271 | return power; |
| 272 | } |
| 273 | |
| 274 | static int get_cores_per_package(void) |
| 275 | { |
| 276 | struct cpuinfo_x86 c; |
| 277 | struct cpuid_result result; |
| 278 | int cores = 1; |
| 279 | |
| 280 | get_fms(&c, cpuid_eax(1)); |
| 281 | if (c.x86 != 6) |
| 282 | return 1; |
| 283 | |
| 284 | result = cpuid_ext(0xb, 1); |
| 285 | cores = result.ebx & 0xff; |
| 286 | |
| 287 | return cores; |
| 288 | } |
| 289 | |
| 290 | static void generate_c_state_entries(void) |
| 291 | { |
| 292 | acpi_cstate_t *c_state_map; |
| 293 | size_t entries; |
| 294 | |
| 295 | c_state_map = soc_get_cstate_map(&entries); |
| 296 | |
| 297 | /* Generate C-state tables */ |
| 298 | acpigen_write_CST_package(c_state_map, entries); |
| 299 | } |
| 300 | |
| 301 | void generate_p_state_entries(int core, int cores_per_package) |
| 302 | { |
| 303 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 304 | int coord_type, power_max, num_entries; |
| 305 | int ratio, power, clock, clock_max; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 306 | bool turbo; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 307 | |
| 308 | coord_type = cpu_get_coord_type(); |
| 309 | ratio_min = cpu_get_min_ratio(); |
| 310 | ratio_max = cpu_get_max_ratio(); |
| 311 | clock_max = (ratio_max * cpu_get_bus_clock()) / KHz; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 312 | turbo = (get_turbo_state() == TURBO_ENABLED); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 313 | |
| 314 | /* Calculate CPU TDP in mW */ |
| 315 | power_max = cpu_get_power_max(); |
| 316 | |
| 317 | /* Write _PCT indicating use of FFixedHW */ |
| 318 | acpigen_write_empty_PCT(); |
| 319 | |
| 320 | /* Write _PPC with no limit on supported P-state */ |
| 321 | acpigen_write_PPC_NVS(); |
| 322 | /* Write PSD indicating configured coordination type */ |
| 323 | acpigen_write_PSD_package(core, 1, coord_type); |
| 324 | |
| 325 | /* Add P-state entries in _PSS table */ |
| 326 | acpigen_write_name("_PSS"); |
| 327 | |
| 328 | /* Determine ratio points */ |
| 329 | ratio_step = PSS_RATIO_STEP; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 330 | do { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 331 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 332 | if (((ratio_max - ratio_min) % ratio_step) > 0) |
| 333 | num_entries += 1; |
| 334 | if (turbo) |
| 335 | num_entries += 1; |
| 336 | if (num_entries > PSS_MAX_ENTRIES) |
| 337 | ratio_step += 1; |
| 338 | } while (num_entries > PSS_MAX_ENTRIES); |
| 339 | |
| 340 | /* _PSS package count depends on Turbo */ |
| 341 | acpigen_write_package(num_entries); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 342 | |
| 343 | /* P[T] is Turbo state if enabled */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 344 | if (turbo) { |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 345 | ratio_turbo = cpu_get_max_turbo_ratio(); |
| 346 | |
| 347 | /* Add entry for Turbo ratio */ |
| 348 | acpigen_write_PSS_package(clock_max + 1, /* MHz */ |
| 349 | power_max, /* mW */ |
| 350 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 351 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 352 | ratio_turbo << 8, /* control */ |
| 353 | ratio_turbo << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 354 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | /* First regular entry is max non-turbo ratio */ |
| 358 | acpigen_write_PSS_package(clock_max, /* MHz */ |
| 359 | power_max, /* mW */ |
| 360 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 361 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 362 | ratio_max << 8, /* control */ |
| 363 | ratio_max << 8); /* status */ |
Julien Viard de Galbert | c2540a9 | 2018-11-06 09:28:03 +0100 | [diff] [blame] | 364 | num_entries -= 1; |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 365 | |
| 366 | /* Generate the remaining entries */ |
| 367 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 368 | ratio >= ratio_min; ratio -= ratio_step) { |
| 369 | |
| 370 | /* Calculate power at this ratio */ |
| 371 | power = calculate_power(power_max, ratio_max, ratio); |
| 372 | clock = (ratio * cpu_get_bus_clock()) / KHz; |
| 373 | |
| 374 | acpigen_write_PSS_package(clock, /* MHz */ |
| 375 | power, /* mW */ |
| 376 | PSS_LATENCY_TRANSITION,/* lat1 */ |
| 377 | PSS_LATENCY_BUSMASTER,/* lat2 */ |
| 378 | ratio << 8, /* control */ |
| 379 | ratio << 8); /* status */ |
| 380 | } |
| 381 | /* Fix package length */ |
| 382 | acpigen_pop_len(); |
| 383 | } |
| 384 | |
Julien Viard de Galbert | 595202c | 2018-03-29 14:01:01 +0200 | [diff] [blame] | 385 | __attribute__ ((weak)) acpi_tstate_t *soc_get_tss_table(int *entries) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 386 | { |
| 387 | *entries = 0; |
| 388 | return NULL; |
| 389 | } |
| 390 | |
| 391 | void generate_t_state_entries(int core, int cores_per_package) |
| 392 | { |
| 393 | acpi_tstate_t *soc_tss_table; |
| 394 | int entries; |
| 395 | |
| 396 | soc_tss_table = soc_get_tss_table(&entries); |
| 397 | if (entries == 0) |
| 398 | return; |
| 399 | |
| 400 | /* Indicate SW_ALL coordination for T-states */ |
| 401 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
| 402 | |
| 403 | /* Indicate FixedHW so OS will use MSR */ |
| 404 | acpigen_write_empty_PTC(); |
| 405 | |
| 406 | /* Set NVS controlled T-state limit */ |
| 407 | acpigen_write_TPC("\\TLVL"); |
| 408 | |
| 409 | /* Write TSS table for MSR access */ |
| 410 | acpigen_write_TSS_package(entries, soc_tss_table); |
| 411 | } |
| 412 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 413 | __weak void soc_power_states_generation(int core_id, |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 414 | int cores_per_package) |
| 415 | { |
| 416 | } |
| 417 | |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 418 | void generate_cpu_entries(struct device *device) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 419 | { |
| 420 | int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; |
| 421 | int plen = 6; |
| 422 | int totalcores = dev_count_cpu(); |
| 423 | int cores_per_package = get_cores_per_package(); |
| 424 | int numcpus = totalcores / cores_per_package; |
| 425 | |
| 426 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 427 | numcpus, cores_per_package); |
| 428 | |
| 429 | for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { |
| 430 | for (core_id = 0; core_id < cores_per_package; core_id++) { |
| 431 | if (core_id > 0) { |
| 432 | pcontrol_blk = 0; |
| 433 | plen = 0; |
| 434 | } |
| 435 | |
| 436 | /* Generate processor \_PR.CPUx */ |
| 437 | acpigen_write_processor((cpu_id) * cores_per_package + |
| 438 | core_id, pcontrol_blk, plen); |
| 439 | |
| 440 | /* Generate C-state tables */ |
| 441 | generate_c_state_entries(); |
| 442 | |
| 443 | /* Soc specific power states generation */ |
| 444 | soc_power_states_generation(core_id, cores_per_package); |
| 445 | |
| 446 | acpigen_pop_len(); |
| 447 | } |
| 448 | } |
Arthur Heymans | 0ac555e | 2018-11-28 12:25:54 +0100 | [diff] [blame] | 449 | /* PPKG is usually used for thermal management |
| 450 | of the first and only package. */ |
| 451 | acpigen_write_processor_package("PPKG", 0, cores_per_package); |
| 452 | |
| 453 | /* Add a method to notify processor nodes */ |
| 454 | acpigen_write_processor_cnot(cores_per_package); |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 455 | } |
| 456 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 457 | #if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame] | 458 | /* Save wake source data for ACPI _SWS methods in NVS */ |
| 459 | static void acpi_save_wake_source(void *unused) |
| 460 | { |
| 461 | global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 462 | uint32_t pm1, *gpe0; |
| 463 | int gpe_reg, gpe_reg_count; |
| 464 | int reg_size = sizeof(uint32_t) * 8; |
| 465 | |
| 466 | if (!gnvs) |
| 467 | return; |
| 468 | |
| 469 | gnvs->pm1i = -1; |
| 470 | gnvs->gpei = -1; |
| 471 | |
| 472 | gpe_reg_count = acpi_fill_wake(&pm1, &gpe0); |
| 473 | if (gpe_reg_count < 0) |
| 474 | return; |
| 475 | |
| 476 | /* Scan for first set bit in PM1 */ |
| 477 | for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) { |
| 478 | if (pm1 & 1) |
| 479 | break; |
| 480 | pm1 >>= 1; |
| 481 | } |
| 482 | |
| 483 | /* If unable to determine then return -1 */ |
| 484 | if (gnvs->pm1i >= 16) |
| 485 | gnvs->pm1i = -1; |
| 486 | |
| 487 | /* Scan for first set bit in GPE registers */ |
| 488 | for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) { |
| 489 | uint32_t gpe = gpe0[gpe_reg]; |
| 490 | int start = gpe_reg * reg_size; |
| 491 | int end = start + reg_size; |
| 492 | |
| 493 | if (gpe == 0) { |
| 494 | if (!gnvs->gpei) |
| 495 | gnvs->gpei = end; |
| 496 | continue; |
| 497 | } |
| 498 | |
| 499 | for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { |
| 500 | if (gpe & 1) |
| 501 | break; |
| 502 | gpe >>= 1; |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | /* If unable to determine then return -1 */ |
| 507 | if (gnvs->gpei >= gpe_reg_count * reg_size) |
| 508 | gnvs->gpei = -1; |
| 509 | |
| 510 | printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", |
| 511 | (long long)gnvs->pm1i, (long long)gnvs->gpei); |
| 512 | } |
| 513 | |
| 514 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); |
| 515 | |
| 516 | #endif |