Blame - src/soc/intel/xeon_sp/cpx/Kconfig - coreboot

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Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	1	## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	2
				3	if SOC_INTEL_COOPERLAKE_SP
				4
Arthur Heymans	86d195b	2020-12-11 09:46:03 +0100	[diff] [blame]	5	config SOC_SPECIFIC_OPTIONS
				6	def_bool y
				7	select MICROCODE_BLOB_NOT_HOOKED_UP
				8
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	9	config FSP_HEADER_PATH
				10	string "Location of FSP headers"
				11	depends on MAINBOARD_USES_FSP2_0
				12	default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
				13
				14	config MAX_SOCKET
				15	int
				16	default 2
				17
				18	config MAX_CPUS
				19	int
Andrey Petrov	e37d1f7	2020-04-20 21:11:51 -0700	[diff] [blame]	20	default 255
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	21
Christian Walter	19df8d8	2020-09-30 13:44:02 +0200	[diff] [blame]	22	config CPU_ADDR_BITS
				23	int
				24	default 46
				25
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	26	config PCR_BASE_ADDRESS
				27	hex
				28	default 0xfd000000
				29	help
				30	This option allows you to select MMIO Base Address of sideband bus.
				31
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	32	config DCACHE_RAM_BASE
				33	hex
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	34	default 0xfe800000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	35
				36	config DCACHE_RAM_SIZE
				37	hex
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	38	default 0x1fff00
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	39	help
				40	The size of the cache-as-ram region required during bootblock
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	41	and/or romstage. FSP-T reserves the upper 0x100 for
				42	FspReservedBuffer.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	43
				44	config DCACHE_BSP_STACK_SIZE
				45	hex
Arthur Heymans	7a5c369	2021-01-04 12:49:39 +0100	[diff] [blame]	46	default 0x40000
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	47	help
				48	The amount of anticipated stack usage in CAR by bootblock and
				49	other stages. It needs to include FSP-M stack requirement and
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	50	CB romstage stack requirement. The integration documentation
Arthur Heymans	7a5c369	2021-01-04 12:49:39 +0100	[diff] [blame]	51	says this needs to be 256KiB.
				52
				53	config FSP_M_RC_HEAP_SIZE
				54	hex
				55	default 0x130000
				56	help
				57	On xeon_sp/cpx FSP-M has two separate heap managers, one regular
				58	whose size and base are controllable via the StackBase and
				59	StackSize UPDs and a 'rc' heap manager that is statically
				60	allocated at 0xfe800000 (the CAR base) and consumes about 0x130000
				61	bytes of memory.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	62
				63	config CPU_MICROCODE_CBFS_LOC
				64	hex
				65	default 0xfff0fdc0
				66
				67	config CPU_MICROCODE_CBFS_LEN
				68	hex
				69	default 0x7C00
				70
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	71	config HEAP_SIZE
				72	hex
				73	default 0x80000
				74
Jonathan Zhang	4337a9a	2020-07-31 17:35:25 -0700	[diff] [blame]	75	config STACK_SIZE
				76	hex
				77	default 0x4000
				78
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	79	config FSP_TEMP_RAM_SIZE
				80	hex
				81	depends on FSP_USES_CB_STACK
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	82	default 0x40000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	83	help
				84	The amount of anticipated heap usage in CAR by FSP.
				85	Refer to Platform FSP integration guide document to know
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	86	the exact FSP requirement for Heap setup. The FSP integration
				87	documentation says this needs to be at least 128KiB, but practice
				88	show this needs to be 256KiB or more.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	89
Rocky Phagura	17a798b	2020-10-08 13:32:41 -0700	[diff] [blame]	90	config IED_REGION_SIZE
				91	hex
				92	default 0x400000
				93
Johnny Lin	c05aa26	2021-06-22 11:35:41 +0800	[diff] [blame^]	94	config IFD_CHIPSET
				95	string
				96	default "lbg"
				97
Andrey Petrov	cf270f0	2020-04-30 13:36:38 -0700	[diff] [blame]	98	config SOC_INTEL_COMMON_BLOCK_P2SB
				99	def_bool y
				100
Jingle Hsu	a41b12c	2020-08-11 20:48:45 +0800	[diff] [blame]	101	config CPU_BCLK_MHZ
				102	int
				103	default 100
				104
Jonathan Zhang	decf7dc	2020-07-27 15:26:30 -0700	[diff] [blame]	105	# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
				106	# Default value is set to one socket, full config.
				107	config DIMM_MAX
				108	int
				109	default 12
				110
				111	# DDR4
				112	config DIMM_SPD_SIZE
				113	int
				114	default 512
				115
Arthur Heymans	9059a89	2020-10-23 11:08:41 +0200	[diff] [blame]	116	if INTEL_TXT
				117
				118	config INTEL_TXT_SINIT_SIZE
				119	hex
				120	default 0x50000
				121	help
				122	According to document number 572782 this needs to be 256KiB
				123	for the SINIT module and 64KiB for SINIT data.
				124
				125	config INTEL_TXT_HEAP_SIZE
				126	hex
				127	default 0xf0000
				128	help
				129	This must be 960KiB according to 572782.
				130
				131	endif # INTEL_TXT
				132
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	133	endif