Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 2 | |
| 3 | if SOC_INTEL_COOPERLAKE_SP |
| 4 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 5 | config FSP_HEADER_PATH |
| 6 | string "Location of FSP headers" |
| 7 | depends on MAINBOARD_USES_FSP2_0 |
| 8 | default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp" |
| 9 | |
| 10 | config MAX_SOCKET |
| 11 | int |
| 12 | default 2 |
| 13 | |
| 14 | config MAX_CPUS |
| 15 | int |
Andrey Petrov | e37d1f7 | 2020-04-20 21:11:51 -0700 | [diff] [blame] | 16 | default 255 |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 17 | |
Christian Walter | 19df8d8 | 2020-09-30 13:44:02 +0200 | [diff] [blame^] | 18 | config CPU_ADDR_BITS |
| 19 | int |
| 20 | default 46 |
| 21 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 22 | config PCR_BASE_ADDRESS |
| 23 | hex |
| 24 | default 0xfd000000 |
| 25 | help |
| 26 | This option allows you to select MMIO Base Address of sideband bus. |
| 27 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 28 | config DCACHE_RAM_BASE |
| 29 | hex |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 30 | default 0xfe8b0000 |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 31 | |
| 32 | config DCACHE_RAM_SIZE |
| 33 | hex |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 34 | default 0x170000 |
| 35 | help |
| 36 | The size of the cache-as-ram region required during bootblock |
| 37 | and/or romstage. |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 38 | |
| 39 | config DCACHE_BSP_STACK_SIZE |
| 40 | hex |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 41 | default 0xA0000 |
| 42 | help |
| 43 | The amount of anticipated stack usage in CAR by bootblock and |
| 44 | other stages. It needs to include FSP-M stack requirement and |
| 45 | CB romstage stack requirement. |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 46 | |
| 47 | config CPU_MICROCODE_CBFS_LOC |
| 48 | hex |
| 49 | default 0xfff0fdc0 |
| 50 | |
| 51 | config CPU_MICROCODE_CBFS_LEN |
| 52 | hex |
| 53 | default 0x7C00 |
| 54 | |
| 55 | config C_ENV_BOOTBLOCK_SIZE |
| 56 | hex |
| 57 | default 0xC000 |
| 58 | |
| 59 | config HEAP_SIZE |
| 60 | hex |
| 61 | default 0x80000 |
| 62 | |
Jonathan Zhang | 4337a9a | 2020-07-31 17:35:25 -0700 | [diff] [blame] | 63 | config STACK_SIZE |
| 64 | hex |
| 65 | default 0x4000 |
| 66 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 67 | config FSP_TEMP_RAM_SIZE |
| 68 | hex |
| 69 | depends on FSP_USES_CB_STACK |
Jonathan Zhang | d4efb33 | 2020-07-22 12:39:40 -0700 | [diff] [blame] | 70 | default 0xA0000 |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 71 | help |
| 72 | The amount of anticipated heap usage in CAR by FSP. |
| 73 | Refer to Platform FSP integration guide document to know |
| 74 | the exact FSP requirement for Heap setup. |
| 75 | |
Andrey Petrov | cf270f0 | 2020-04-30 13:36:38 -0700 | [diff] [blame] | 76 | config SOC_INTEL_COMMON_BLOCK_P2SB |
| 77 | def_bool y |
| 78 | |
Jingle Hsu | a41b12c | 2020-08-11 20:48:45 +0800 | [diff] [blame] | 79 | config CPU_BCLK_MHZ |
| 80 | int |
| 81 | default 100 |
| 82 | |
Jonathan Zhang | decf7dc | 2020-07-27 15:26:30 -0700 | [diff] [blame] | 83 | # CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel |
| 84 | # Default value is set to one socket, full config. |
| 85 | config DIMM_MAX |
| 86 | int |
| 87 | default 12 |
| 88 | |
| 89 | # DDR4 |
| 90 | config DIMM_SPD_SIZE |
| 91 | int |
| 92 | default 512 |
| 93 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 94 | endif |