Blame - src/soc/intel/xeon_sp/cpx/Kconfig - coreboot

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Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	1	## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	2
				3	if SOC_INTEL_COOPERLAKE_SP
				4
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	5	config FSP_HEADER_PATH
				6	string "Location of FSP headers"
				7	depends on MAINBOARD_USES_FSP2_0
				8	default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
				9
				10	config MAX_SOCKET
				11	int
				12	default 2
				13
				14	config MAX_CPUS
				15	int
Andrey Petrov	e37d1f7	2020-04-20 21:11:51 -0700	[diff] [blame]	16	default 255
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	17
				18	config PCR_BASE_ADDRESS
				19	hex
				20	default 0xfd000000
				21	help
				22	This option allows you to select MMIO Base Address of sideband bus.
				23
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	24	config DCACHE_RAM_BASE
				25	hex
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	26	default 0xfe8b0000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	27
				28	config DCACHE_RAM_SIZE
				29	hex
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	30	default 0x170000
				31	help
				32	The size of the cache-as-ram region required during bootblock
				33	and/or romstage.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	34
				35	config DCACHE_BSP_STACK_SIZE
				36	hex
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	37	default 0xA0000
				38	help
				39	The amount of anticipated stack usage in CAR by bootblock and
				40	other stages. It needs to include FSP-M stack requirement and
				41	CB romstage stack requirement.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	42
				43	config CPU_MICROCODE_CBFS_LOC
				44	hex
				45	default 0xfff0fdc0
				46
				47	config CPU_MICROCODE_CBFS_LEN
				48	hex
				49	default 0x7C00
				50
				51	config C_ENV_BOOTBLOCK_SIZE
				52	hex
				53	default 0xC000
				54
				55	config HEAP_SIZE
				56	hex
				57	default 0x80000
				58
Jonathan Zhang	4337a9a	2020-07-31 17:35:25 -0700	[diff] [blame^]	59	config STACK_SIZE
				60	hex
				61	default 0x4000
				62
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	63	config FSP_TEMP_RAM_SIZE
				64	hex
				65	depends on FSP_USES_CB_STACK
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	66	default 0xA0000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	67	help
				68	The amount of anticipated heap usage in CAR by FSP.
				69	Refer to Platform FSP integration guide document to know
				70	the exact FSP requirement for Heap setup.
				71
Andrey Petrov	cf270f0	2020-04-30 13:36:38 -0700	[diff] [blame]	72	config SOC_INTEL_COMMON_BLOCK_P2SB
				73	def_bool y
				74
Jonathan Zhang	7454005	2020-06-01 16:01:08 -0700	[diff] [blame]	75	select CACHE_MRC_SETTINGS
				76
Jonathan Zhang	decf7dc	2020-07-27 15:26:30 -0700	[diff] [blame]	77	# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
				78	# Default value is set to one socket, full config.
				79	config DIMM_MAX
				80	int
				81	default 12
				82
				83	# DDR4
				84	config DIMM_SPD_SIZE
				85	int
				86	default 512
				87
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	88	endif