Blame - src/soc/intel/xeon_sp/cpx/Kconfig - coreboot

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Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	1	## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	2
				3	if SOC_INTEL_COOPERLAKE_SP
				4
				5	config MAINBOARD_USES_FSP2_0
				6	bool
				7	default y
				8
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	9	config FSP_HEADER_PATH
				10	string "Location of FSP headers"
				11	depends on MAINBOARD_USES_FSP2_0
				12	default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
				13
				14	config MAX_SOCKET
				15	int
				16	default 2
				17
				18	config MAX_CPUS
				19	int
Andrey Petrov	e37d1f7	2020-04-20 21:11:51 -0700	[diff] [blame]	20	default 255
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	21
				22	config PCR_BASE_ADDRESS
				23	hex
				24	default 0xfd000000
				25	help
				26	This option allows you to select MMIO Base Address of sideband bus.
				27
				28	# currently FSP hardcodes [0fe800000;fe930000] for its heap
				29	config DCACHE_RAM_BASE
				30	hex
Andrey Petrov	dddb9a8	2020-04-20 18:07:08 -0700	[diff] [blame]	31	default 0xfe9a0000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	32
				33	config DCACHE_RAM_SIZE
				34	hex
Andrey Petrov	dddb9a8	2020-04-20 18:07:08 -0700	[diff] [blame]	35	default 0x60000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	36
				37	config DCACHE_BSP_STACK_SIZE
				38	hex
				39	default 0x10000
				40
				41	config CPU_MICROCODE_CBFS_LOC
				42	hex
				43	default 0xfff0fdc0
				44
				45	config CPU_MICROCODE_CBFS_LEN
				46	hex
				47	default 0x7C00
				48
				49	config C_ENV_BOOTBLOCK_SIZE
				50	hex
				51	default 0xC000
				52
				53	config HEAP_SIZE
				54	hex
				55	default 0x80000
				56
				57	config FSP_TEMP_RAM_SIZE
				58	hex
				59	depends on FSP_USES_CB_STACK
				60	default 0x70000
				61	help
				62	The amount of anticipated heap usage in CAR by FSP.
				63	Refer to Platform FSP integration guide document to know
				64	the exact FSP requirement for Heap setup.
				65
Andrey Petrov	cf270f0	2020-04-30 13:36:38 -0700	[diff] [blame]	66	config SOC_INTEL_COMMON_BLOCK_P2SB
				67	def_bool y
				68
Jonathan Zhang	7454005	2020-06-01 16:01:08 -0700	[diff] [blame]	69	select CACHE_MRC_SETTINGS
				70
Jonathan Zhang	decf7dc	2020-07-27 15:26:30 -0700	[diff] [blame^]	71	# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
				72	# Default value is set to one socket, full config.
				73	config DIMM_MAX
				74	int
				75	default 12
				76
				77	# DDR4
				78	config DIMM_SPD_SIZE
				79	int
				80	default 512
				81
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	82	endif