Blame - src/soc/intel/xeon_sp/cpx/Kconfig - coreboot

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Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	1	## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	2
				3	if SOC_INTEL_COOPERLAKE_SP
				4
Arthur Heymans	86d195b	2020-12-11 09:46:03 +0100	[diff] [blame]	5	config SOC_SPECIFIC_OPTIONS
				6	def_bool y
				7	select MICROCODE_BLOB_NOT_HOOKED_UP
				8
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	9	config FSP_HEADER_PATH
				10	string "Location of FSP headers"
				11	depends on MAINBOARD_USES_FSP2_0
				12	default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
				13
				14	config MAX_SOCKET
				15	int
				16	default 2
				17
				18	config MAX_CPUS
				19	int
Andrey Petrov	e37d1f7	2020-04-20 21:11:51 -0700	[diff] [blame]	20	default 255
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	21
Christian Walter	19df8d8	2020-09-30 13:44:02 +0200	[diff] [blame]	22	config CPU_ADDR_BITS
				23	int
				24	default 46
				25
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	26	config PCR_BASE_ADDRESS
				27	hex
				28	default 0xfd000000
				29	help
				30	This option allows you to select MMIO Base Address of sideband bus.
				31
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	32	config DCACHE_RAM_BASE
				33	hex
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	34	default 0xfe800000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	35
				36	config DCACHE_RAM_SIZE
				37	hex
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	38	default 0x1fff00
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	39	help
				40	The size of the cache-as-ram region required during bootblock
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	41	and/or romstage. FSP-T reserves the upper 0x100 for
				42	FspReservedBuffer.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	43
				44	config DCACHE_BSP_STACK_SIZE
				45	hex
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	46	default 0x140000
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	47	help
				48	The amount of anticipated stack usage in CAR by bootblock and
				49	other stages. It needs to include FSP-M stack requirement and
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	50	CB romstage stack requirement. The integration documentation
				51	says this needs to be 256KiB, but practice show this needs to
				52	be a lot more.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	53
				54	config CPU_MICROCODE_CBFS_LOC
				55	hex
				56	default 0xfff0fdc0
				57
				58	config CPU_MICROCODE_CBFS_LEN
				59	hex
				60	default 0x7C00
				61
				62	config C_ENV_BOOTBLOCK_SIZE
				63	hex
				64	default 0xC000
				65
				66	config HEAP_SIZE
				67	hex
				68	default 0x80000
				69
Jonathan Zhang	4337a9a	2020-07-31 17:35:25 -0700	[diff] [blame]	70	config STACK_SIZE
				71	hex
				72	default 0x4000
				73
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	74	config FSP_TEMP_RAM_SIZE
				75	hex
				76	depends on FSP_USES_CB_STACK
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	77	default 0x40000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	78	help
				79	The amount of anticipated heap usage in CAR by FSP.
				80	Refer to Platform FSP integration guide document to know
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	81	the exact FSP requirement for Heap setup. The FSP integration
				82	documentation says this needs to be at least 128KiB, but practice
				83	show this needs to be 256KiB or more.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	84
Rocky Phagura	17a798b	2020-10-08 13:32:41 -0700	[diff] [blame]	85	config IED_REGION_SIZE
				86	hex
				87	default 0x400000
				88
Andrey Petrov	cf270f0	2020-04-30 13:36:38 -0700	[diff] [blame]	89	config SOC_INTEL_COMMON_BLOCK_P2SB
				90	def_bool y
				91
Jingle Hsu	a41b12c	2020-08-11 20:48:45 +0800	[diff] [blame]	92	config CPU_BCLK_MHZ
				93	int
				94	default 100
				95
Jonathan Zhang	decf7dc	2020-07-27 15:26:30 -0700	[diff] [blame]	96	# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
				97	# Default value is set to one socket, full config.
				98	config DIMM_MAX
				99	int
				100	default 12
				101
				102	# DDR4
				103	config DIMM_SPD_SIZE
				104	int
				105	default 512
				106
Arthur Heymans	9059a89	2020-10-23 11:08:41 +0200	[diff] [blame^]	107	if INTEL_TXT
				108
				109	config INTEL_TXT_SINIT_SIZE
				110	hex
				111	default 0x50000
				112	help
				113	According to document number 572782 this needs to be 256KiB
				114	for the SINIT module and 64KiB for SINIT data.
				115
				116	config INTEL_TXT_HEAP_SIZE
				117	hex
				118	default 0xf0000
				119	help
				120	This must be 960KiB according to 572782.
				121
				122	endif # INTEL_TXT
				123
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	124	endif