blob: 70703d0c7856450bb744695b3d36c25304031017 [file] [log] [blame]
Andrey Petrov2e410752020-03-20 12:08:32 -07001##
2## SPDX-License-Identifier: GPL-2.0-only
3## This file is part of the coreboot project.
4##
5
6if SOC_INTEL_COOPERLAKE_SP
7
8config MAINBOARD_USES_FSP2_0
9 bool
10 default y
11
12config USE_FSP2_0_DRIVER
13 def_bool y
14 depends on MAINBOARD_USES_FSP2_0
15 select PLATFORM_USES_FSP2_0
16 select UDK_2015_BINDING
17 select POSTCAR_CONSOLE
18 select POSTCAR_STAGE
19 select FSP_USES_CB_STACK
20
21config FSP_HEADER_PATH
22 string "Location of FSP headers"
23 depends on MAINBOARD_USES_FSP2_0
24 default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
25
26config MAX_SOCKET
27 int
28 default 2
29
30config MAX_CPUS
31 int
32 default 80
33
34config PCR_BASE_ADDRESS
35 hex
36 default 0xfd000000
37 help
38 This option allows you to select MMIO Base Address of sideband bus.
39
40# currently FSP hardcodes [0fe800000;fe930000] for its heap
41config DCACHE_RAM_BASE
42 hex
43 default 0xfe930000
44
45config DCACHE_RAM_SIZE
46 hex
47 default 0xd0000
48
49config DCACHE_BSP_STACK_SIZE
50 hex
51 default 0x10000
52
53config CPU_MICROCODE_CBFS_LOC
54 hex
55 default 0xfff0fdc0
56
57config CPU_MICROCODE_CBFS_LEN
58 hex
59 default 0x7C00
60
61config C_ENV_BOOTBLOCK_SIZE
62 hex
63 default 0xC000
64
65config HEAP_SIZE
66 hex
67 default 0x80000
68
69config FSP_TEMP_RAM_SIZE
70 hex
71 depends on FSP_USES_CB_STACK
72 default 0x70000
73 help
74 The amount of anticipated heap usage in CAR by FSP.
75 Refer to Platform FSP integration guide document to know
76 the exact FSP requirement for Heap setup.
77
78endif