soc/intel/xeon_sp: Add basic Cooperlake-SP support
This adds barebones support.
What works:
* Linux kernel boots fine
* SIRQ and PCH interupts work fine (only in IOAPIC mode)
* PCH devices are usable
What doesn't:
* MP init is not there yet, only 1 CPU is up
* SMM is not supported
* GPIO is not available
* All IIO and extended bus numbers enumeration is not yet available
* Warm reset flow is untested
* MRC cache save/load
TEST=boots into Linux
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
new file mode 100644
index 0000000..70703d0
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -0,0 +1,78 @@
+##
+## SPDX-License-Identifier: GPL-2.0-only
+## This file is part of the coreboot project.
+##
+
+if SOC_INTEL_COOPERLAKE_SP
+
+config MAINBOARD_USES_FSP2_0
+ bool
+ default y
+
+config USE_FSP2_0_DRIVER
+ def_bool y
+ depends on MAINBOARD_USES_FSP2_0
+ select PLATFORM_USES_FSP2_0
+ select UDK_2015_BINDING
+ select POSTCAR_CONSOLE
+ select POSTCAR_STAGE
+ select FSP_USES_CB_STACK
+
+config FSP_HEADER_PATH
+ string "Location of FSP headers"
+ depends on MAINBOARD_USES_FSP2_0
+ default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
+
+config MAX_SOCKET
+ int
+ default 2
+
+config MAX_CPUS
+ int
+ default 80
+
+config PCR_BASE_ADDRESS
+ hex
+ default 0xfd000000
+ help
+ This option allows you to select MMIO Base Address of sideband bus.
+
+# currently FSP hardcodes [0fe800000;fe930000] for its heap
+config DCACHE_RAM_BASE
+ hex
+ default 0xfe930000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0xd0000
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x10000
+
+config CPU_MICROCODE_CBFS_LOC
+ hex
+ default 0xfff0fdc0
+
+config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x7C00
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0xC000
+
+config HEAP_SIZE
+ hex
+ default 0x80000
+
+config FSP_TEMP_RAM_SIZE
+ hex
+ depends on FSP_USES_CB_STACK
+ default 0x70000
+ help
+ The amount of anticipated heap usage in CAR by FSP.
+ Refer to Platform FSP integration guide document to know
+ the exact FSP requirement for Heap setup.
+
+endif