Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 2 | |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 3 | #include <arch/mmu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <delay.h> |
| 8 | #include <edid.h> |
| 9 | #include <gpio.h> |
Elyes HAOUAS | 0badea8 | 2020-07-10 10:43:24 +0200 | [diff] [blame] | 10 | #include <stdint.h> |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 11 | #include <soc/addressmap.h> |
| 12 | #include <soc/clock.h> |
| 13 | #include <soc/display.h> |
| 14 | #include <soc/edp.h> |
| 15 | #include <soc/gpio.h> |
| 16 | #include <soc/grf.h> |
| 17 | #include <soc/mmu_operations.h> |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 18 | #include <soc/mipi.h> |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 19 | #include <soc/soc.h> |
| 20 | #include <soc/vop.h> |
Patrick Rudolph | 8b56c8c | 2020-02-19 12:57:00 +0100 | [diff] [blame] | 21 | #include <framebuffer_info.h> |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 22 | |
| 23 | #include "chip.h" |
| 24 | |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 25 | static void reset_edp(void) |
| 26 | { |
| 27 | /* rst edp */ |
| 28 | write32(&cru_ptr->softrst_con[17], |
| 29 | RK_SETBITS(1 << 12 | 1 << 13)); |
| 30 | udelay(1); |
| 31 | write32(&cru_ptr->softrst_con[17], |
| 32 | RK_CLRBITS(1 << 12 | 1 << 13)); |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 33 | printk(BIOS_WARNING, "Retrying EDP initialization.\n"); |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 34 | } |
| 35 | |
Elyes HAOUAS | f3ca88b | 2018-05-25 09:52:45 +0200 | [diff] [blame] | 36 | void rk_display_init(struct device *dev) |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 37 | { |
| 38 | struct edid edid; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 39 | struct soc_rockchip_rk3399_config *conf = dev->chip_info; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 40 | enum vop_modes detected_mode = VOP_MODE_UNKNOWN; |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 41 | const struct mipi_panel_data *panel_data = NULL; |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 42 | int retry_count_init = 0; |
| 43 | int retry_count_edp_prepare = 0; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 44 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 45 | /* let's use vop0 in rk3399 */ |
| 46 | uint32_t vop_id = 0; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 47 | |
| 48 | switch (conf->vop_mode) { |
| 49 | case VOP_MODE_NONE: |
| 50 | return; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 51 | case VOP_MODE_EDP: |
| 52 | printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 53 | rkclk_configure_vop_aclk(vop_id, 200 * MHz); |
Lin Huang | 4ecccff | 2017-01-18 09:44:34 +0800 | [diff] [blame] | 54 | rkclk_configure_edp(25 * MHz); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 55 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 56 | /* select edp signal from vop0 */ |
| 57 | write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5)); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 58 | |
| 59 | /* select edp clk from SoC internal 24M crystal, otherwise, |
| 60 | * it will source from edp's 24M clock (that depends on |
| 61 | * edp vendor, could be unstable) |
| 62 | */ |
| 63 | write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); |
| 64 | |
Lin Huang | 079b5c6 | 2016-11-21 17:35:20 +0800 | [diff] [blame] | 65 | retry_edp: |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 66 | /* Reset in case code jumped here. */ |
| 67 | retry_count_init = 0; |
| 68 | while (retry_count_init++ < 3) { |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 69 | rk_edp_init(); |
| 70 | if (rk_edp_get_edid(&edid) == 0) { |
| 71 | detected_mode = VOP_MODE_EDP; |
| 72 | break; |
| 73 | } |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 74 | if (retry_count_init == 3) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 75 | printk(BIOS_WARNING, "EDP initialization failed.\n"); |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 76 | return; |
| 77 | } else { |
| 78 | reset_edp(); |
| 79 | } |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 80 | } |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 81 | break; |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 82 | case VOP_MODE_MIPI: |
| 83 | printk(BIOS_DEBUG, "Attempting to setup MIPI display.\n"); |
| 84 | |
| 85 | rkclk_configure_mipi(); |
| 86 | rkclk_configure_vop_aclk(vop_id, 200 * MHz); |
| 87 | |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 88 | /* |
| 89 | * disable tx0 turnrequest, turndisable, |
| 90 | * forcetxstop, forcerxmode |
| 91 | */ |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 92 | write32(&rk3399_grf->soc_con22, RK_CLRBITS(0xffff)); |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 93 | |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 94 | /* disable tx1 turndisable, forcetxstop, forcerxmode */ |
| 95 | write32(&rk3399_grf->soc_con23, RK_CLRBITS(0xfff0)); |
| 96 | |
| 97 | /* |
| 98 | * enable dphy_tx1rx1_masterslavez, |
| 99 | * clear dphy_tx1rx1_enableclk, |
| 100 | * clear dphy_tx1rx1_basedir, |
| 101 | * disable tx1 turnrequest |
| 102 | */ |
| 103 | write32(&rk3399_grf->soc_con24, |
| 104 | RK_CLRSETBITS(1 << 7 | 1 << 6 | 1 << 5 | 0xf, |
| 105 | 1 << 7 | 0 << 6 | 0 << 5 | 0 << 0)); |
| 106 | |
| 107 | /* dphy_tx1rx1_enable */ |
| 108 | write32(&rk3399_grf->soc_con23, RK_SETBITS(0xf)); |
| 109 | |
| 110 | /* select mipi-dsi0 and mipi-dsi1 signal from vop0 */ |
| 111 | write32(&rk3399_grf->soc_con20, |
| 112 | RK_CLRBITS((1 << 0) | (1 << 4))); |
| 113 | |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 114 | panel_data = mainboard_get_mipi_mode(&edid.mode); |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 115 | if (panel_data) { |
| 116 | if (panel_data->mipi_num > 1) |
| 117 | detected_mode = VOP_MODE_DUAL_MIPI; |
| 118 | else |
| 119 | detected_mode = VOP_MODE_MIPI; |
| 120 | } else { |
| 121 | printk(BIOS_WARNING, "Can not get mipi panel data\n"); |
| 122 | return; |
| 123 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 124 | break; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 125 | default: |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 126 | printk(BIOS_WARNING, "Unsupported vop_mode, aborting.\n"); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 127 | return; |
| 128 | } |
| 129 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 130 | if (rkclk_configure_vop_dclk(vop_id, |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 131 | edid.mode.pixel_clock * KHz)) { |
| 132 | printk(BIOS_WARNING, "config vop err\n"); |
| 133 | return; |
| 134 | } |
| 135 | |
Julius Werner | e74f5ea | 2016-10-17 18:14:41 -0700 | [diff] [blame] | 136 | edid_set_framebuffer_bits_per_pixel(&edid, |
| 137 | conf->framebuffer_bits_per_pixel, 0); |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 138 | rkvop_mode_set(vop_id, &edid, detected_mode); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 139 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 140 | rkvop_prepare(vop_id, &edid); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 141 | |
| 142 | switch (detected_mode) { |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 143 | case VOP_MODE_MIPI: |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 144 | case VOP_MODE_DUAL_MIPI: |
| 145 | rk_mipi_prepare(&edid, panel_data); |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 146 | break; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 147 | case VOP_MODE_EDP: |
Lin Huang | a09b338 | 2016-10-23 14:17:25 -0700 | [diff] [blame] | 148 | /* will enable edp in depthcharge */ |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 149 | if (rk_edp_prepare()) { |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 150 | if (retry_count_edp_prepare++ < 3) { |
| 151 | reset_edp(); |
| 152 | /* Rerun entire init sequence */ |
| 153 | goto retry_edp; |
| 154 | } |
| 155 | printk(BIOS_ERR, "EDP preparation failed."); |
| 156 | return; |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 157 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 158 | break; |
| 159 | default: |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 160 | break; |
| 161 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 162 | mainboard_power_on_backlight(); |
Patrick Rudolph | 8b56c8c | 2020-02-19 12:57:00 +0100 | [diff] [blame] | 163 | fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 164 | } |