blob: 5199bf3d34e36dc5c29eddd79261fa4dea6ffc82 [file] [log] [blame]
Shunqian Zhengd1cec752016-05-04 16:21:36 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/cache.h>
17#include <arch/mmu.h>
18#include <arch/io.h>
19#include <console/console.h>
20#include <device/device.h>
21#include <delay.h>
22#include <edid.h>
23#include <gpio.h>
24#include <stdlib.h>
25#include <stddef.h>
26#include <string.h>
27#include <soc/addressmap.h>
28#include <soc/clock.h>
29#include <soc/display.h>
30#include <soc/edp.h>
31#include <soc/gpio.h>
32#include <soc/grf.h>
33#include <soc/mmu_operations.h>
34#include <soc/soc.h>
35#include <soc/vop.h>
36
37#include "chip.h"
38
Martin Rothe4b9af12016-11-29 10:50:52 -070039static void reset_edp(void)
40{
41 /* rst edp */
42 write32(&cru_ptr->softrst_con[17],
43 RK_SETBITS(1 << 12 | 1 << 13));
44 udelay(1);
45 write32(&cru_ptr->softrst_con[17],
46 RK_CLRBITS(1 << 12 | 1 << 13));
47 printk(BIOS_WARNING, "Retrying epd initialization.\n");
48}
49
Lin Huang152e6752016-10-20 14:22:11 -070050void rk_display_init(device_t dev)
Shunqian Zhengd1cec752016-05-04 16:21:36 +080051{
52 struct edid edid;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080053 struct soc_rockchip_rk3399_config *conf = dev->chip_info;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080054 enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
Lin Huang079b5c62016-11-21 17:35:20 +080055 int retry_count = 0;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080056
Lin Huang152e6752016-10-20 14:22:11 -070057 /* let's use vop0 in rk3399 */
58 uint32_t vop_id = 0;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080059
60 switch (conf->vop_mode) {
61 case VOP_MODE_NONE:
62 return;
63 case VOP_MODE_AUTO_DETECT:
64 /* try EDP first, then HDMI */
65 case VOP_MODE_EDP:
66 printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
Julius Werner8e42bd1c2016-11-01 15:24:54 -070067 rkclk_configure_vop_aclk(vop_id, 200 * MHz);
Shunqian Zhengd1cec752016-05-04 16:21:36 +080068
Lin Huang152e6752016-10-20 14:22:11 -070069 /* select edp signal from vop0 */
70 write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
Shunqian Zhengd1cec752016-05-04 16:21:36 +080071
72 /* select edp clk from SoC internal 24M crystal, otherwise,
73 * it will source from edp's 24M clock (that depends on
74 * edp vendor, could be unstable)
75 */
76 write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11));
77
Lin Huang079b5c62016-11-21 17:35:20 +080078retry_edp:
Martin Rothe4b9af12016-11-29 10:50:52 -070079 while (retry_count++ < 3) {
80 rk_edp_init();
81 if (rk_edp_get_edid(&edid) == 0) {
82 detected_mode = VOP_MODE_EDP;
83 break;
84 }
85 if (retry_count == 3) {
86 printk(BIOS_WARNING, "Warning: epd initialization failed.\n");
87 return;
88 } else {
89 reset_edp();
90 }
Shunqian Zhengd1cec752016-05-04 16:21:36 +080091 }
Martin Rothe4b9af12016-11-29 10:50:52 -070092 break;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080093 case VOP_MODE_HDMI:
94 printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n");
95 return;
96 default:
97 printk(BIOS_WARNING, "Cannot read any EDID info, aborting.\n");
98 return;
99 }
100
Lin Huang152e6752016-10-20 14:22:11 -0700101 if (rkclk_configure_vop_dclk(vop_id,
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800102 edid.mode.pixel_clock * KHz)) {
103 printk(BIOS_WARNING, "config vop err\n");
104 return;
105 }
106
Julius Wernere74f5ea2016-10-17 18:14:41 -0700107 edid_set_framebuffer_bits_per_pixel(&edid,
108 conf->framebuffer_bits_per_pixel, 0);
Lin Huang152e6752016-10-20 14:22:11 -0700109 rkvop_mode_set(vop_id, &edid, detected_mode);
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800110
Lin Huang152e6752016-10-20 14:22:11 -0700111 rkvop_prepare(vop_id, &edid);
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800112
113 switch (detected_mode) {
114 case VOP_MODE_HDMI:
115 /* should not be here before HDMI supported */
116 return;
117 case VOP_MODE_EDP:
118 default:
Lin Huanga09b3382016-10-23 14:17:25 -0700119 /* will enable edp in depthcharge */
Martin Rothe4b9af12016-11-29 10:50:52 -0700120 if (rk_edp_prepare()) {
121 reset_edp();
122 goto retry_edp; /* Rerun entire init sequence */
123 }
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800124 mainboard_power_on_backlight();
125 break;
126 }
127
Lin Huang152e6752016-10-20 14:22:11 -0700128 set_vbe_mode_info_valid(&edid, (uintptr_t)0);
Lin Huang079b5c62016-11-21 17:35:20 +0800129 return;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800130}