blob: 4261b263991113742d9d0038c51fb24cb04d700e [file] [log] [blame]
Shunqian Zhengd1cec752016-05-04 16:21:36 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/cache.h>
17#include <arch/mmu.h>
18#include <arch/io.h>
19#include <console/console.h>
20#include <device/device.h>
21#include <delay.h>
22#include <edid.h>
23#include <gpio.h>
24#include <stdlib.h>
25#include <stddef.h>
26#include <string.h>
27#include <soc/addressmap.h>
28#include <soc/clock.h>
29#include <soc/display.h>
30#include <soc/edp.h>
31#include <soc/gpio.h>
32#include <soc/grf.h>
33#include <soc/mmu_operations.h>
34#include <soc/soc.h>
35#include <soc/vop.h>
36
37#include "chip.h"
38
Lin Huang152e6752016-10-20 14:22:11 -070039void rk_display_init(device_t dev)
Shunqian Zhengd1cec752016-05-04 16:21:36 +080040{
41 struct edid edid;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080042 struct soc_rockchip_rk3399_config *conf = dev->chip_info;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080043 enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
Lin Huang079b5c62016-11-21 17:35:20 +080044 int retry_count = 0;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080045
Lin Huang152e6752016-10-20 14:22:11 -070046 /* let's use vop0 in rk3399 */
47 uint32_t vop_id = 0;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080048
49 switch (conf->vop_mode) {
50 case VOP_MODE_NONE:
51 return;
52 case VOP_MODE_AUTO_DETECT:
53 /* try EDP first, then HDMI */
54 case VOP_MODE_EDP:
55 printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
Julius Werner8e42bd1c2016-11-01 15:24:54 -070056 rkclk_configure_vop_aclk(vop_id, 200 * MHz);
Shunqian Zhengd1cec752016-05-04 16:21:36 +080057
Lin Huang152e6752016-10-20 14:22:11 -070058 /* select edp signal from vop0 */
59 write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
Shunqian Zhengd1cec752016-05-04 16:21:36 +080060
61 /* select edp clk from SoC internal 24M crystal, otherwise,
62 * it will source from edp's 24M clock (that depends on
63 * edp vendor, could be unstable)
64 */
65 write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11));
66
Lin Huang079b5c62016-11-21 17:35:20 +080067retry_edp:
Shunqian Zhengd1cec752016-05-04 16:21:36 +080068 rk_edp_init();
Shunqian Zhengd1cec752016-05-04 16:21:36 +080069 if (rk_edp_get_edid(&edid) == 0) {
70 detected_mode = VOP_MODE_EDP;
71 break;
72 }
Lin Huang079b5c62016-11-21 17:35:20 +080073 goto edp_error;
74
Shunqian Zhengd1cec752016-05-04 16:21:36 +080075 /* fall thru */
76 case VOP_MODE_HDMI:
77 printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n");
78 return;
79 default:
80 printk(BIOS_WARNING, "Cannot read any EDID info, aborting.\n");
81 return;
82 }
83
Lin Huang152e6752016-10-20 14:22:11 -070084 if (rkclk_configure_vop_dclk(vop_id,
Shunqian Zhengd1cec752016-05-04 16:21:36 +080085 edid.mode.pixel_clock * KHz)) {
86 printk(BIOS_WARNING, "config vop err\n");
87 return;
88 }
89
Julius Wernere74f5ea2016-10-17 18:14:41 -070090 edid_set_framebuffer_bits_per_pixel(&edid,
91 conf->framebuffer_bits_per_pixel, 0);
Lin Huang152e6752016-10-20 14:22:11 -070092 rkvop_mode_set(vop_id, &edid, detected_mode);
Shunqian Zhengd1cec752016-05-04 16:21:36 +080093
Lin Huang152e6752016-10-20 14:22:11 -070094 rkvop_prepare(vop_id, &edid);
Shunqian Zhengd1cec752016-05-04 16:21:36 +080095
96 switch (detected_mode) {
97 case VOP_MODE_HDMI:
98 /* should not be here before HDMI supported */
99 return;
100 case VOP_MODE_EDP:
101 default:
Lin Huanga09b3382016-10-23 14:17:25 -0700102 /* will enable edp in depthcharge */
Lin Huang079b5c62016-11-21 17:35:20 +0800103 if (rk_edp_prepare())
104 goto edp_error;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800105 mainboard_power_on_backlight();
106 break;
107 }
108
Lin Huang152e6752016-10-20 14:22:11 -0700109 set_vbe_mode_info_valid(&edid, (uintptr_t)0);
Lin Huang079b5c62016-11-21 17:35:20 +0800110 return;
111
112edp_error:
113 if (retry_count++ < 3) {
114 /* rst edp */
115 write32(&cru_ptr->softrst_con[17],
116 RK_SETBITS(1 << 12 | 1 << 13));
117 udelay(1);
118 write32(&cru_ptr->softrst_con[17],
119 RK_CLRBITS(1 << 12 | 1 << 13));
120 goto retry_edp;
121 }
122 printk(BIOS_WARNING, "epd initial error\n");
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800123}