Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/cache.h> |
| 17 | #include <arch/mmu.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <delay.h> |
| 22 | #include <edid.h> |
| 23 | #include <gpio.h> |
| 24 | #include <stdlib.h> |
| 25 | #include <stddef.h> |
| 26 | #include <string.h> |
| 27 | #include <soc/addressmap.h> |
| 28 | #include <soc/clock.h> |
| 29 | #include <soc/display.h> |
| 30 | #include <soc/edp.h> |
| 31 | #include <soc/gpio.h> |
| 32 | #include <soc/grf.h> |
| 33 | #include <soc/mmu_operations.h> |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 34 | #include <soc/mipi.h> |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 35 | #include <soc/soc.h> |
| 36 | #include <soc/vop.h> |
| 37 | |
| 38 | #include "chip.h" |
| 39 | |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 40 | static void reset_edp(void) |
| 41 | { |
| 42 | /* rst edp */ |
| 43 | write32(&cru_ptr->softrst_con[17], |
| 44 | RK_SETBITS(1 << 12 | 1 << 13)); |
| 45 | udelay(1); |
| 46 | write32(&cru_ptr->softrst_con[17], |
| 47 | RK_CLRBITS(1 << 12 | 1 << 13)); |
| 48 | printk(BIOS_WARNING, "Retrying epd initialization.\n"); |
| 49 | } |
| 50 | |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 51 | static void rk_get_mipi_mode(struct edid *edid, device_t dev) |
| 52 | { |
| 53 | struct soc_rockchip_rk3399_config *conf = dev->chip_info; |
| 54 | |
| 55 | edid->mode.pixel_clock = conf->panel_pixel_clock; |
| 56 | edid->mode.refresh = conf->panel_refresh; |
| 57 | edid->mode.ha = conf->panel_ha; |
| 58 | edid->mode.hbl = conf->panel_hbl; |
| 59 | edid->mode.hso = conf->panel_hso; |
| 60 | edid->mode.hspw = conf->panel_hspw; |
| 61 | edid->mode.va = conf->panel_va; |
| 62 | edid->mode.vbl = conf->panel_vbl; |
| 63 | edid->mode.vso = conf->panel_vso; |
| 64 | edid->mode.vspw = conf->panel_vspw; |
| 65 | } |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 66 | void rk_display_init(device_t dev) |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 67 | { |
| 68 | struct edid edid; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 69 | struct soc_rockchip_rk3399_config *conf = dev->chip_info; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 70 | enum vop_modes detected_mode = VOP_MODE_UNKNOWN; |
Lin Huang | 079b5c6 | 2016-11-21 17:35:20 +0800 | [diff] [blame] | 71 | int retry_count = 0; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 72 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 73 | /* let's use vop0 in rk3399 */ |
| 74 | uint32_t vop_id = 0; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 75 | |
| 76 | switch (conf->vop_mode) { |
| 77 | case VOP_MODE_NONE: |
| 78 | return; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 79 | case VOP_MODE_EDP: |
| 80 | printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 81 | rkclk_configure_vop_aclk(vop_id, 200 * MHz); |
Lin Huang | 4ecccff | 2017-01-18 09:44:34 +0800 | [diff] [blame] | 82 | rkclk_configure_edp(25 * MHz); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 83 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 84 | /* select edp signal from vop0 */ |
| 85 | write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5)); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 86 | |
| 87 | /* select edp clk from SoC internal 24M crystal, otherwise, |
| 88 | * it will source from edp's 24M clock (that depends on |
| 89 | * edp vendor, could be unstable) |
| 90 | */ |
| 91 | write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); |
| 92 | |
Lin Huang | 079b5c6 | 2016-11-21 17:35:20 +0800 | [diff] [blame] | 93 | retry_edp: |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 94 | while (retry_count++ < 3) { |
| 95 | rk_edp_init(); |
| 96 | if (rk_edp_get_edid(&edid) == 0) { |
| 97 | detected_mode = VOP_MODE_EDP; |
| 98 | break; |
| 99 | } |
| 100 | if (retry_count == 3) { |
| 101 | printk(BIOS_WARNING, "Warning: epd initialization failed.\n"); |
| 102 | return; |
| 103 | } else { |
| 104 | reset_edp(); |
| 105 | } |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 106 | } |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 107 | break; |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 108 | case VOP_MODE_MIPI: |
| 109 | printk(BIOS_DEBUG, "Attempting to setup MIPI display.\n"); |
| 110 | |
| 111 | rkclk_configure_mipi(); |
| 112 | rkclk_configure_vop_aclk(vop_id, 200 * MHz); |
| 113 | |
| 114 | /* disable turnrequest turndisable forcetxstop forcerxmode */ |
| 115 | write32(&rk3399_grf->soc_con22, RK_CLRBITS(0xffff)); |
| 116 | /* select mipi-dsi0 signal from vop0 */ |
| 117 | write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 0)); |
| 118 | |
| 119 | rk_get_mipi_mode(&edid, dev); |
| 120 | detected_mode = VOP_MODE_MIPI; |
| 121 | break; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 122 | default: |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 123 | printk(BIOS_WARNING, "Unsupported vop_mode, aborting.\n"); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 124 | return; |
| 125 | } |
| 126 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 127 | if (rkclk_configure_vop_dclk(vop_id, |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 128 | edid.mode.pixel_clock * KHz)) { |
| 129 | printk(BIOS_WARNING, "config vop err\n"); |
| 130 | return; |
| 131 | } |
| 132 | |
Julius Werner | e74f5ea | 2016-10-17 18:14:41 -0700 | [diff] [blame] | 133 | edid_set_framebuffer_bits_per_pixel(&edid, |
| 134 | conf->framebuffer_bits_per_pixel, 0); |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 135 | rkvop_mode_set(vop_id, &edid, detected_mode); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 136 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 137 | rkvop_prepare(vop_id, &edid); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 138 | |
| 139 | switch (detected_mode) { |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 140 | case VOP_MODE_MIPI: |
| 141 | rk_mipi_prepare(&edid, conf->panel_display_on_mdelay, conf->panel_video_mode_mdelay); |
| 142 | break; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 143 | case VOP_MODE_EDP: |
Lin Huang | a09b338 | 2016-10-23 14:17:25 -0700 | [diff] [blame] | 144 | /* will enable edp in depthcharge */ |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 145 | if (rk_edp_prepare()) { |
| 146 | reset_edp(); |
| 147 | goto retry_edp; /* Rerun entire init sequence */ |
| 148 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 149 | break; |
| 150 | default: |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 151 | break; |
| 152 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 153 | mainboard_power_on_backlight(); |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 154 | set_vbe_mode_info_valid(&edid, (uintptr_t)0); |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame^] | 155 | |
Lin Huang | 079b5c6 | 2016-11-21 17:35:20 +0800 | [diff] [blame] | 156 | return; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 157 | } |