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Shunqian Zhengd1cec752016-05-04 16:21:36 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/cache.h>
17#include <arch/mmu.h>
18#include <arch/io.h>
19#include <console/console.h>
20#include <device/device.h>
21#include <delay.h>
22#include <edid.h>
23#include <gpio.h>
24#include <stdlib.h>
25#include <stddef.h>
26#include <string.h>
27#include <soc/addressmap.h>
28#include <soc/clock.h>
29#include <soc/display.h>
30#include <soc/edp.h>
31#include <soc/gpio.h>
32#include <soc/grf.h>
33#include <soc/mmu_operations.h>
Nickey Yangfe122d42017-04-27 09:38:06 +080034#include <soc/mipi.h>
Shunqian Zhengd1cec752016-05-04 16:21:36 +080035#include <soc/soc.h>
36#include <soc/vop.h>
37
38#include "chip.h"
39
Martin Rothe4b9af12016-11-29 10:50:52 -070040static void reset_edp(void)
41{
42 /* rst edp */
43 write32(&cru_ptr->softrst_con[17],
44 RK_SETBITS(1 << 12 | 1 << 13));
45 udelay(1);
46 write32(&cru_ptr->softrst_con[17],
47 RK_CLRBITS(1 << 12 | 1 << 13));
48 printk(BIOS_WARNING, "Retrying epd initialization.\n");
49}
50
Nickey Yangfe122d42017-04-27 09:38:06 +080051static void rk_get_mipi_mode(struct edid *edid, device_t dev)
52{
53 struct soc_rockchip_rk3399_config *conf = dev->chip_info;
54
55 edid->mode.pixel_clock = conf->panel_pixel_clock;
56 edid->mode.refresh = conf->panel_refresh;
57 edid->mode.ha = conf->panel_ha;
58 edid->mode.hbl = conf->panel_hbl;
59 edid->mode.hso = conf->panel_hso;
60 edid->mode.hspw = conf->panel_hspw;
61 edid->mode.va = conf->panel_va;
62 edid->mode.vbl = conf->panel_vbl;
63 edid->mode.vso = conf->panel_vso;
64 edid->mode.vspw = conf->panel_vspw;
65}
Lin Huang152e6752016-10-20 14:22:11 -070066void rk_display_init(device_t dev)
Shunqian Zhengd1cec752016-05-04 16:21:36 +080067{
68 struct edid edid;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080069 struct soc_rockchip_rk3399_config *conf = dev->chip_info;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080070 enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
Lin Huang079b5c62016-11-21 17:35:20 +080071 int retry_count = 0;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080072
Lin Huang152e6752016-10-20 14:22:11 -070073 /* let's use vop0 in rk3399 */
74 uint32_t vop_id = 0;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080075
76 switch (conf->vop_mode) {
77 case VOP_MODE_NONE:
78 return;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080079 case VOP_MODE_EDP:
80 printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
Julius Werner8e42bd1c2016-11-01 15:24:54 -070081 rkclk_configure_vop_aclk(vop_id, 200 * MHz);
Lin Huang4ecccff2017-01-18 09:44:34 +080082 rkclk_configure_edp(25 * MHz);
Shunqian Zhengd1cec752016-05-04 16:21:36 +080083
Lin Huang152e6752016-10-20 14:22:11 -070084 /* select edp signal from vop0 */
85 write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
Shunqian Zhengd1cec752016-05-04 16:21:36 +080086
87 /* select edp clk from SoC internal 24M crystal, otherwise,
88 * it will source from edp's 24M clock (that depends on
89 * edp vendor, could be unstable)
90 */
91 write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11));
92
Lin Huang079b5c62016-11-21 17:35:20 +080093retry_edp:
Martin Rothe4b9af12016-11-29 10:50:52 -070094 while (retry_count++ < 3) {
95 rk_edp_init();
96 if (rk_edp_get_edid(&edid) == 0) {
97 detected_mode = VOP_MODE_EDP;
98 break;
99 }
100 if (retry_count == 3) {
101 printk(BIOS_WARNING, "Warning: epd initialization failed.\n");
102 return;
103 } else {
104 reset_edp();
105 }
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800106 }
Martin Rothe4b9af12016-11-29 10:50:52 -0700107 break;
Nickey Yangfe122d42017-04-27 09:38:06 +0800108 case VOP_MODE_MIPI:
109 printk(BIOS_DEBUG, "Attempting to setup MIPI display.\n");
110
111 rkclk_configure_mipi();
112 rkclk_configure_vop_aclk(vop_id, 200 * MHz);
113
114 /* disable turnrequest turndisable forcetxstop forcerxmode */
115 write32(&rk3399_grf->soc_con22, RK_CLRBITS(0xffff));
116 /* select mipi-dsi0 signal from vop0 */
117 write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 0));
118
119 rk_get_mipi_mode(&edid, dev);
120 detected_mode = VOP_MODE_MIPI;
121 break;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800122 default:
Nickey Yangfe122d42017-04-27 09:38:06 +0800123 printk(BIOS_WARNING, "Unsupported vop_mode, aborting.\n");
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800124 return;
125 }
126
Lin Huang152e6752016-10-20 14:22:11 -0700127 if (rkclk_configure_vop_dclk(vop_id,
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800128 edid.mode.pixel_clock * KHz)) {
129 printk(BIOS_WARNING, "config vop err\n");
130 return;
131 }
132
Julius Wernere74f5ea2016-10-17 18:14:41 -0700133 edid_set_framebuffer_bits_per_pixel(&edid,
134 conf->framebuffer_bits_per_pixel, 0);
Lin Huang152e6752016-10-20 14:22:11 -0700135 rkvop_mode_set(vop_id, &edid, detected_mode);
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800136
Lin Huang152e6752016-10-20 14:22:11 -0700137 rkvop_prepare(vop_id, &edid);
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800138
139 switch (detected_mode) {
Nickey Yangfe122d42017-04-27 09:38:06 +0800140 case VOP_MODE_MIPI:
141 rk_mipi_prepare(&edid, conf->panel_display_on_mdelay, conf->panel_video_mode_mdelay);
142 break;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800143 case VOP_MODE_EDP:
Lin Huanga09b3382016-10-23 14:17:25 -0700144 /* will enable edp in depthcharge */
Martin Rothe4b9af12016-11-29 10:50:52 -0700145 if (rk_edp_prepare()) {
146 reset_edp();
147 goto retry_edp; /* Rerun entire init sequence */
148 }
Nickey Yangfe122d42017-04-27 09:38:06 +0800149 break;
150 default:
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800151 break;
152 }
Nickey Yangfe122d42017-04-27 09:38:06 +0800153 mainboard_power_on_backlight();
Lin Huang152e6752016-10-20 14:22:11 -0700154 set_vbe_mode_info_valid(&edid, (uintptr_t)0);
Nickey Yangfe122d42017-04-27 09:38:06 +0800155
Lin Huang079b5c62016-11-21 17:35:20 +0800156 return;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800157}