Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/cache.h> |
| 17 | #include <arch/mmu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame^] | 18 | #include <device/mmio.h> |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <delay.h> |
| 22 | #include <edid.h> |
| 23 | #include <gpio.h> |
| 24 | #include <stdlib.h> |
| 25 | #include <stddef.h> |
| 26 | #include <string.h> |
| 27 | #include <soc/addressmap.h> |
| 28 | #include <soc/clock.h> |
| 29 | #include <soc/display.h> |
| 30 | #include <soc/edp.h> |
| 31 | #include <soc/gpio.h> |
| 32 | #include <soc/grf.h> |
| 33 | #include <soc/mmu_operations.h> |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 34 | #include <soc/mipi.h> |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 35 | #include <soc/soc.h> |
| 36 | #include <soc/vop.h> |
| 37 | |
| 38 | #include "chip.h" |
| 39 | |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 40 | static void reset_edp(void) |
| 41 | { |
| 42 | /* rst edp */ |
| 43 | write32(&cru_ptr->softrst_con[17], |
| 44 | RK_SETBITS(1 << 12 | 1 << 13)); |
| 45 | udelay(1); |
| 46 | write32(&cru_ptr->softrst_con[17], |
| 47 | RK_CLRBITS(1 << 12 | 1 << 13)); |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 48 | printk(BIOS_WARNING, "Retrying EDP initialization.\n"); |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 49 | } |
| 50 | |
Elyes HAOUAS | f3ca88b | 2018-05-25 09:52:45 +0200 | [diff] [blame] | 51 | void rk_display_init(struct device *dev) |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 52 | { |
| 53 | struct edid edid; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 54 | struct soc_rockchip_rk3399_config *conf = dev->chip_info; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 55 | enum vop_modes detected_mode = VOP_MODE_UNKNOWN; |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 56 | const struct mipi_panel_data *panel_data = NULL; |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 57 | int retry_count_init = 0; |
| 58 | int retry_count_edp_prepare = 0; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 59 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 60 | /* let's use vop0 in rk3399 */ |
| 61 | uint32_t vop_id = 0; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 62 | |
| 63 | switch (conf->vop_mode) { |
| 64 | case VOP_MODE_NONE: |
| 65 | return; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 66 | case VOP_MODE_EDP: |
| 67 | printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); |
Julius Werner | 8e42bd1c | 2016-11-01 15:24:54 -0700 | [diff] [blame] | 68 | rkclk_configure_vop_aclk(vop_id, 200 * MHz); |
Lin Huang | 4ecccff | 2017-01-18 09:44:34 +0800 | [diff] [blame] | 69 | rkclk_configure_edp(25 * MHz); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 70 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 71 | /* select edp signal from vop0 */ |
| 72 | write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5)); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 73 | |
| 74 | /* select edp clk from SoC internal 24M crystal, otherwise, |
| 75 | * it will source from edp's 24M clock (that depends on |
| 76 | * edp vendor, could be unstable) |
| 77 | */ |
| 78 | write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); |
| 79 | |
Lin Huang | 079b5c6 | 2016-11-21 17:35:20 +0800 | [diff] [blame] | 80 | retry_edp: |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 81 | /* Reset in case code jumped here. */ |
| 82 | retry_count_init = 0; |
| 83 | while (retry_count_init++ < 3) { |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 84 | rk_edp_init(); |
| 85 | if (rk_edp_get_edid(&edid) == 0) { |
| 86 | detected_mode = VOP_MODE_EDP; |
| 87 | break; |
| 88 | } |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 89 | if (retry_count_init == 3) { |
| 90 | printk(BIOS_WARNING, |
| 91 | "Warning: EDP initialization failed.\n"); |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 92 | return; |
| 93 | } else { |
| 94 | reset_edp(); |
| 95 | } |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 96 | } |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 97 | break; |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 98 | case VOP_MODE_MIPI: |
| 99 | printk(BIOS_DEBUG, "Attempting to setup MIPI display.\n"); |
| 100 | |
| 101 | rkclk_configure_mipi(); |
| 102 | rkclk_configure_vop_aclk(vop_id, 200 * MHz); |
| 103 | |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 104 | /* |
| 105 | * disable tx0 turnrequest, turndisable, |
| 106 | * forcetxstop, forcerxmode |
| 107 | */ |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 108 | write32(&rk3399_grf->soc_con22, RK_CLRBITS(0xffff)); |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 109 | |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 110 | /* disable tx1 turndisable, forcetxstop, forcerxmode */ |
| 111 | write32(&rk3399_grf->soc_con23, RK_CLRBITS(0xfff0)); |
| 112 | |
| 113 | /* |
| 114 | * enable dphy_tx1rx1_masterslavez, |
| 115 | * clear dphy_tx1rx1_enableclk, |
| 116 | * clear dphy_tx1rx1_basedir, |
| 117 | * disable tx1 turnrequest |
| 118 | */ |
| 119 | write32(&rk3399_grf->soc_con24, |
| 120 | RK_CLRSETBITS(1 << 7 | 1 << 6 | 1 << 5 | 0xf, |
| 121 | 1 << 7 | 0 << 6 | 0 << 5 | 0 << 0)); |
| 122 | |
| 123 | /* dphy_tx1rx1_enable */ |
| 124 | write32(&rk3399_grf->soc_con23, RK_SETBITS(0xf)); |
| 125 | |
| 126 | /* select mipi-dsi0 and mipi-dsi1 signal from vop0 */ |
| 127 | write32(&rk3399_grf->soc_con20, |
| 128 | RK_CLRBITS((1 << 0) | (1 << 4))); |
| 129 | |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 130 | panel_data = mainboard_get_mipi_mode(&edid.mode); |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 131 | if (panel_data) { |
| 132 | if (panel_data->mipi_num > 1) |
| 133 | detected_mode = VOP_MODE_DUAL_MIPI; |
| 134 | else |
| 135 | detected_mode = VOP_MODE_MIPI; |
| 136 | } else { |
| 137 | printk(BIOS_WARNING, "Can not get mipi panel data\n"); |
| 138 | return; |
| 139 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 140 | break; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 141 | default: |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 142 | printk(BIOS_WARNING, "Unsupported vop_mode, aborting.\n"); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 143 | return; |
| 144 | } |
| 145 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 146 | if (rkclk_configure_vop_dclk(vop_id, |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 147 | edid.mode.pixel_clock * KHz)) { |
| 148 | printk(BIOS_WARNING, "config vop err\n"); |
| 149 | return; |
| 150 | } |
| 151 | |
Julius Werner | e74f5ea | 2016-10-17 18:14:41 -0700 | [diff] [blame] | 152 | edid_set_framebuffer_bits_per_pixel(&edid, |
| 153 | conf->framebuffer_bits_per_pixel, 0); |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 154 | rkvop_mode_set(vop_id, &edid, detected_mode); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 155 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 156 | rkvop_prepare(vop_id, &edid); |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 157 | |
| 158 | switch (detected_mode) { |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 159 | case VOP_MODE_MIPI: |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 160 | case VOP_MODE_DUAL_MIPI: |
| 161 | rk_mipi_prepare(&edid, panel_data); |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 162 | break; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 163 | case VOP_MODE_EDP: |
Lin Huang | a09b338 | 2016-10-23 14:17:25 -0700 | [diff] [blame] | 164 | /* will enable edp in depthcharge */ |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 165 | if (rk_edp_prepare()) { |
Ege Mihmanli | bb9bdeb | 2018-01-07 18:03:07 -0800 | [diff] [blame] | 166 | if (retry_count_edp_prepare++ < 3) { |
| 167 | reset_edp(); |
| 168 | /* Rerun entire init sequence */ |
| 169 | goto retry_edp; |
| 170 | } |
| 171 | printk(BIOS_ERR, "EDP preparation failed."); |
| 172 | return; |
Martin Roth | e4b9af1 | 2016-11-29 10:50:52 -0700 | [diff] [blame] | 173 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 174 | break; |
| 175 | default: |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 176 | break; |
| 177 | } |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 178 | mainboard_power_on_backlight(); |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 179 | set_vbe_mode_info_valid(&edid, (uintptr_t)0); |
Nickey Yang | fe122d4 | 2017-04-27 09:38:06 +0800 | [diff] [blame] | 180 | |
Lin Huang | 079b5c6 | 2016-11-21 17:35:20 +0800 | [diff] [blame] | 181 | return; |
Shunqian Zheng | d1cec75 | 2016-05-04 16:21:36 +0800 | [diff] [blame] | 182 | } |