rockchip/rk3399: set edp pclk to 25MHz
It may cause an edp aux transfer error if the edp pclk is
set too high, so reduce it to 25MHz.
BUG=chrome-os-partner:60130
BRANCH=None
TEST=Build and Boot
Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596
Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/429410
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c
index 5199bf3d..c7ca891 100644
--- a/src/soc/rockchip/rk3399/display.c
+++ b/src/soc/rockchip/rk3399/display.c
@@ -65,6 +65,7 @@
case VOP_MODE_EDP:
printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
rkclk_configure_vop_aclk(vop_id, 200 * MHz);
+ rkclk_configure_edp(25 * MHz);
/* select edp signal from vop0 */
write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));