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Shunqian Zhengd1cec752016-05-04 16:21:36 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/cache.h>
17#include <arch/mmu.h>
18#include <arch/io.h>
19#include <console/console.h>
20#include <device/device.h>
21#include <delay.h>
22#include <edid.h>
23#include <gpio.h>
24#include <stdlib.h>
25#include <stddef.h>
26#include <string.h>
27#include <soc/addressmap.h>
28#include <soc/clock.h>
29#include <soc/display.h>
30#include <soc/edp.h>
31#include <soc/gpio.h>
32#include <soc/grf.h>
33#include <soc/mmu_operations.h>
Nickey Yangfe122d42017-04-27 09:38:06 +080034#include <soc/mipi.h>
Shunqian Zhengd1cec752016-05-04 16:21:36 +080035#include <soc/soc.h>
36#include <soc/vop.h>
37
38#include "chip.h"
39
Martin Rothe4b9af12016-11-29 10:50:52 -070040static void reset_edp(void)
41{
42 /* rst edp */
43 write32(&cru_ptr->softrst_con[17],
44 RK_SETBITS(1 << 12 | 1 << 13));
45 udelay(1);
46 write32(&cru_ptr->softrst_con[17],
47 RK_CLRBITS(1 << 12 | 1 << 13));
48 printk(BIOS_WARNING, "Retrying epd initialization.\n");
49}
50
Lin Huang152e6752016-10-20 14:22:11 -070051void rk_display_init(device_t dev)
Shunqian Zhengd1cec752016-05-04 16:21:36 +080052{
53 struct edid edid;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080054 struct soc_rockchip_rk3399_config *conf = dev->chip_info;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080055 enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
Lin Huang079b5c62016-11-21 17:35:20 +080056 int retry_count = 0;
Lin Huang25fb09b2017-11-22 09:40:50 +080057 const struct mipi_panel_data *panel_data = NULL;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080058
Lin Huang152e6752016-10-20 14:22:11 -070059 /* let's use vop0 in rk3399 */
60 uint32_t vop_id = 0;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080061
62 switch (conf->vop_mode) {
63 case VOP_MODE_NONE:
64 return;
Shunqian Zhengd1cec752016-05-04 16:21:36 +080065 case VOP_MODE_EDP:
66 printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
Julius Werner8e42bd1c2016-11-01 15:24:54 -070067 rkclk_configure_vop_aclk(vop_id, 200 * MHz);
Lin Huang4ecccff2017-01-18 09:44:34 +080068 rkclk_configure_edp(25 * MHz);
Shunqian Zhengd1cec752016-05-04 16:21:36 +080069
Lin Huang152e6752016-10-20 14:22:11 -070070 /* select edp signal from vop0 */
71 write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
Shunqian Zhengd1cec752016-05-04 16:21:36 +080072
73 /* select edp clk from SoC internal 24M crystal, otherwise,
74 * it will source from edp's 24M clock (that depends on
75 * edp vendor, could be unstable)
76 */
77 write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11));
78
Lin Huang079b5c62016-11-21 17:35:20 +080079retry_edp:
Martin Rothe4b9af12016-11-29 10:50:52 -070080 while (retry_count++ < 3) {
81 rk_edp_init();
82 if (rk_edp_get_edid(&edid) == 0) {
83 detected_mode = VOP_MODE_EDP;
84 break;
85 }
86 if (retry_count == 3) {
87 printk(BIOS_WARNING, "Warning: epd initialization failed.\n");
88 return;
89 } else {
90 reset_edp();
91 }
Shunqian Zhengd1cec752016-05-04 16:21:36 +080092 }
Martin Rothe4b9af12016-11-29 10:50:52 -070093 break;
Nickey Yangfe122d42017-04-27 09:38:06 +080094 case VOP_MODE_MIPI:
95 printk(BIOS_DEBUG, "Attempting to setup MIPI display.\n");
96
97 rkclk_configure_mipi();
98 rkclk_configure_vop_aclk(vop_id, 200 * MHz);
99
Lin Huang25fb09b2017-11-22 09:40:50 +0800100 /*
101 * disable tx0 turnrequest, turndisable,
102 * forcetxstop, forcerxmode
103 */
Nickey Yangfe122d42017-04-27 09:38:06 +0800104 write32(&rk3399_grf->soc_con22, RK_CLRBITS(0xffff));
Nickey Yangfe122d42017-04-27 09:38:06 +0800105
Lin Huang25fb09b2017-11-22 09:40:50 +0800106 /* disable tx1 turndisable, forcetxstop, forcerxmode */
107 write32(&rk3399_grf->soc_con23, RK_CLRBITS(0xfff0));
108
109 /*
110 * enable dphy_tx1rx1_masterslavez,
111 * clear dphy_tx1rx1_enableclk,
112 * clear dphy_tx1rx1_basedir,
113 * disable tx1 turnrequest
114 */
115 write32(&rk3399_grf->soc_con24,
116 RK_CLRSETBITS(1 << 7 | 1 << 6 | 1 << 5 | 0xf,
117 1 << 7 | 0 << 6 | 0 << 5 | 0 << 0));
118
119 /* dphy_tx1rx1_enable */
120 write32(&rk3399_grf->soc_con23, RK_SETBITS(0xf));
121
122 /* select mipi-dsi0 and mipi-dsi1 signal from vop0 */
123 write32(&rk3399_grf->soc_con20,
124 RK_CLRBITS((1 << 0) | (1 << 4)));
125
Lin Huangadd76662017-11-23 08:50:03 +0800126 panel_data = mainboard_get_mipi_mode(&edid.mode);
Lin Huang25fb09b2017-11-22 09:40:50 +0800127 if (panel_data) {
128 if (panel_data->mipi_num > 1)
129 detected_mode = VOP_MODE_DUAL_MIPI;
130 else
131 detected_mode = VOP_MODE_MIPI;
132 } else {
133 printk(BIOS_WARNING, "Can not get mipi panel data\n");
134 return;
135 }
Nickey Yangfe122d42017-04-27 09:38:06 +0800136 break;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800137 default:
Nickey Yangfe122d42017-04-27 09:38:06 +0800138 printk(BIOS_WARNING, "Unsupported vop_mode, aborting.\n");
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800139 return;
140 }
141
Lin Huang152e6752016-10-20 14:22:11 -0700142 if (rkclk_configure_vop_dclk(vop_id,
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800143 edid.mode.pixel_clock * KHz)) {
144 printk(BIOS_WARNING, "config vop err\n");
145 return;
146 }
147
Julius Wernere74f5ea2016-10-17 18:14:41 -0700148 edid_set_framebuffer_bits_per_pixel(&edid,
149 conf->framebuffer_bits_per_pixel, 0);
Lin Huang152e6752016-10-20 14:22:11 -0700150 rkvop_mode_set(vop_id, &edid, detected_mode);
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800151
Lin Huang152e6752016-10-20 14:22:11 -0700152 rkvop_prepare(vop_id, &edid);
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800153
154 switch (detected_mode) {
Nickey Yangfe122d42017-04-27 09:38:06 +0800155 case VOP_MODE_MIPI:
Lin Huang25fb09b2017-11-22 09:40:50 +0800156 case VOP_MODE_DUAL_MIPI:
157 rk_mipi_prepare(&edid, panel_data);
Nickey Yangfe122d42017-04-27 09:38:06 +0800158 break;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800159 case VOP_MODE_EDP:
Lin Huanga09b3382016-10-23 14:17:25 -0700160 /* will enable edp in depthcharge */
Martin Rothe4b9af12016-11-29 10:50:52 -0700161 if (rk_edp_prepare()) {
162 reset_edp();
163 goto retry_edp; /* Rerun entire init sequence */
164 }
Nickey Yangfe122d42017-04-27 09:38:06 +0800165 break;
166 default:
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800167 break;
168 }
Nickey Yangfe122d42017-04-27 09:38:06 +0800169 mainboard_power_on_backlight();
Lin Huang152e6752016-10-20 14:22:11 -0700170 set_vbe_mode_info_valid(&edid, (uintptr_t)0);
Nickey Yangfe122d42017-04-27 09:38:06 +0800171
Lin Huang079b5c62016-11-21 17:35:20 +0800172 return;
Shunqian Zhengd1cec752016-05-04 16:21:36 +0800173}