Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 by coresystems GmbH |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 5 | * Copyright (C) 2012 Anton Kochkov |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 6 | * |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame^] | 18 | * Foundation, Inc. |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <stdio.h> |
| 22 | #include <stdlib.h> |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 23 | #include <inttypes.h> |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 24 | #include "inteltool.h" |
| 25 | |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 26 | /* 320766 */ |
| 27 | static const io_register_t nehalem_dmi_registers[] = { |
| 28 | { 0x00, 4, "DMIVCH" }, // DMI Virtual Channel Capability Header |
| 29 | { 0x04, 4, "DMIVCCAP1" }, // DMI Port VC Capability Register 1 |
| 30 | { 0x08, 4, "DMIVCCAP2" }, // DMI Port VC Capability Register 2 |
| 31 | { 0x0C, 4, "DMIVCCTL" }, // DMI Port VC Control |
| 32 | { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability |
| 33 | { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control |
| 34 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 35 | { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status |
| 36 | { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability |
| 37 | { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control |
| 38 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 39 | { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status |
| 40 | /* ... - Reserved */ |
| 41 | { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities |
| 42 | { 0x88, 2, "DMILCTL" }, // DMI Link Control |
| 43 | { 0x8A, 2, "DMILSTS" }, // DMI Link Status |
| 44 | /* ... - Reserved */ |
| 45 | }; |
| 46 | |
| 47 | /* 322812 */ |
| 48 | static const io_register_t westmere_dmi_registers[] = { |
| 49 | { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability |
| 50 | { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 |
| 51 | { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 |
| 52 | { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control |
| 53 | /* { 0x0E, 2, "RSVD" }, // Reserved */ |
| 54 | { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability |
| 55 | { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control |
| 56 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 57 | { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status |
| 58 | { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability |
| 59 | { 0x20, 4, "DMIVC1RCTL1" }, // DMI VC1 Resource Control |
| 60 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 61 | { 0x26, 2, "DMIC1RSTS" }, // DMI VC1 Resource Status |
| 62 | /* ... - Reserved */ |
| 63 | { 0x84, 4, "DMILCAP" }, // DMI Link Capabilities |
| 64 | { 0x88, 2, "DMILCTL" }, // DMI Link Control |
| 65 | { 0x8A, 2, "DMILSTS" }, // DMI Link Status |
| 66 | /* ... - Reserved */ |
| 67 | }; |
| 68 | |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 69 | static const io_register_t sandybridge_dmi_registers[] = { |
| 70 | { 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability |
| 71 | { 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1 |
| 72 | { 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2 |
| 73 | { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control |
| 74 | /* { 0x0E, 2, "RSVD" }, // Reserved */ |
| 75 | { 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability |
| 76 | { 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control |
| 77 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 78 | { 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status |
| 79 | { 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability |
| 80 | { 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control |
| 81 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 82 | { 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status |
| 83 | { 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability |
| 84 | { 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control |
| 85 | /* { 0x30, 2, "RSVD" }, // Reserved */ |
| 86 | { 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status |
| 87 | { 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability |
| 88 | { 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control |
| 89 | /* { 0x3C, 2, "RSVD" }, // Reserved */ |
| 90 | { 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status |
| 91 | /* { 0x40, 4, "RSVD" }, // Reserved */ |
| 92 | { 0x44, 4, "DMI ESC" }, // DMI Element Self Description |
| 93 | /* { 0x48, 8, "RSVD" }, // Reserved */ |
| 94 | { 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description |
| 95 | /* { 0x54, 4, "RSVD" }, // Reserved */ |
| 96 | { 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address |
| 97 | { 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address |
| 98 | { 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description |
| 99 | /* { 0x64, 4, "RSVD" }, // Reserved */ |
| 100 | { 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address |
| 101 | /* { 0x6C, 4, "RSVD" }, // Reserved |
| 102 | { 0x70, 8, "RSVD" }, // Reserved |
| 103 | { 0x78, 8, "RSVD" }, // Reserved |
| 104 | { 0x80, 4, "RSVD" }, // Reserved */ |
| 105 | { 0x84, 4, "LCAP" }, // Link Capabilities |
| 106 | { 0x88, 2, "LCTL" }, // Link Control |
| 107 | { 0x8A, 2, "LSTS" }, // Link Status |
| 108 | /* { 0x8C, 4, "RSVD" }, // Reserved |
| 109 | { 0x90, 4, "RSVD" }, // Reserved |
| 110 | { 0x94, 4, "RSVD" }, // Reserved */ |
| 111 | { 0x98, 2, "LCTL2" }, // Link Control 2 |
| 112 | { 0x9A, 2, "LSTS2" }, // Link Status 2 |
| 113 | /* ... - Reserved */ |
| 114 | { 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0 |
| 115 | { 0xBC4, 4, "RSVD" }, // Reserved |
| 116 | { 0xBC8, 4, "RSVD" }, // Reserved |
| 117 | { 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0 |
| 118 | /* ... - Reserved */ |
| 119 | }; |
| 120 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 121 | /* |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 122 | * All Haswell DMI Registers per |
| 123 | * |
| 124 | * Mobile 4th Generation Intel Core TM Processor Family, Mobile Intel Pentium Processor Family, |
| 125 | * and Mobile Intel Celeron Processor Family |
| 126 | * Datasheet Volume 2 |
| 127 | * 329002-002 |
| 128 | */ |
| 129 | static const io_register_t haswell_ult_dmi_registers[] = { |
| 130 | { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability |
| 131 | { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 |
| 132 | { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 |
| 133 | { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control |
| 134 | /* { 0x0E, 2, "RSVD" }, // Reserved */ |
| 135 | { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability |
| 136 | { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control |
| 137 | /* { 0x18, 2, "RSVD" }, // Reserved */ |
| 138 | { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status |
| 139 | { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability |
| 140 | { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control |
| 141 | /* { 0x24, 2, "RSVD" }, // Reserved */ |
| 142 | { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status |
| 143 | { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability |
| 144 | { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control |
| 145 | /* { 0x30, 2, "RSVD" }, // Reserved */ |
| 146 | { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status |
| 147 | { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability |
| 148 | { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control |
| 149 | /* { 0x3C, 2, "RSVD" }, // Reserved */ |
| 150 | { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status |
| 151 | { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ |
| 152 | { 0x44, 4, "DMIESD" }, // DMI Element Self Description |
| 153 | /* { 0x48, 4, "RSVD" }, // Reserved */ |
| 154 | /* { 0x4C, 4, "RSVD" }, // Reserved */ |
| 155 | { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description |
| 156 | /* { 0x54, 4, "RSVD" }, // Reserved */ |
| 157 | { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address |
| 158 | { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address |
| 159 | { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description |
| 160 | /* { 0x64, 4, "RSVD" }, // Reserved */ |
| 161 | { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address |
| 162 | /* { 0x6C, 4, "RSVD" }, // Reserved */ |
| 163 | /* { 0x70, 4, "RSVD" }, // Reserved */ |
| 164 | /* { 0x74, 4, "RSVD" }, // Reserved */ |
| 165 | /* { 0x78, 4, "RSVD" }, // Reserved */ |
| 166 | /* { 0x7C, 4, "RSVD" }, // Reserved */ |
| 167 | /* { 0x80, 4, "RSVD" }, // Reserved */ |
| 168 | /* { 0x84, 4, "RSVD" }, // Reserved */ |
| 169 | { 0x88, 2, "LCTL" }, // Link Control |
| 170 | /* ... - Reserved */ |
| 171 | { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status |
| 172 | { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask |
| 173 | { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status |
| 174 | { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask |
| 175 | /* ... - Reserved */ |
| 176 | }; |
| 177 | |
| 178 | /* |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 179 | * Egress Port Root Complex MMIO configuration space |
| 180 | */ |
| 181 | int print_epbar(struct pci_dev *nb) |
| 182 | { |
| 183 | int i, size = (4 * 1024); |
| 184 | volatile uint8_t *epbar; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 185 | uint64_t epbar_phys; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 186 | |
| 187 | printf("\n============= EPBAR =============\n\n"); |
| 188 | |
| 189 | switch (nb->device_id) { |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 190 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 191 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 192 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 193 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 194 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 195 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 196 | epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; |
| 197 | break; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 198 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 199 | case PCI_DEVICE_ID_INTEL_82Q965: |
| 200 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 201 | case PCI_DEVICE_ID_INTEL_82G33: |
| 202 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 203 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 204 | case PCI_DEVICE_ID_INTEL_32X0: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 205 | case PCI_DEVICE_ID_INTEL_82X4X: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 206 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 207 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 208 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 209 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
| 210 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
| 211 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
| 212 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 213 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 214 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
| 215 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: |
| 216 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: |
| 217 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 218 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 219 | case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 220 | epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; |
| 221 | epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; |
| 222 | break; |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 223 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 224 | case PCI_DEVICE_ID_INTEL_82810_DC: |
| 225 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 226 | case PCI_DEVICE_ID_INTEL_82830M: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 227 | case PCI_DEVICE_ID_INTEL_82865: |
| 228 | printf("This northbridge does not have EPBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 229 | return 1; |
| 230 | default: |
| 231 | printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); |
| 232 | return 1; |
| 233 | } |
| 234 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 235 | epbar = map_physical(epbar_phys, size); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 236 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 237 | if (epbar == NULL) { |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 238 | perror("Error mapping EPBAR"); |
| 239 | exit(1); |
| 240 | } |
| 241 | |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 242 | printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 243 | for (i = 0; i < size; i += 4) { |
| 244 | if (*(uint32_t *)(epbar + i)) |
| 245 | printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); |
| 246 | } |
| 247 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 248 | unmap_physical((void *)epbar, size); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | /* |
| 253 | * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space |
| 254 | */ |
| 255 | int print_dmibar(struct pci_dev *nb) |
| 256 | { |
| 257 | int i, size = (4 * 1024); |
| 258 | volatile uint8_t *dmibar; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 259 | uint64_t dmibar_phys; |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 260 | const io_register_t *dmi_registers = NULL; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 261 | |
| 262 | printf("\n============= DMIBAR ============\n\n"); |
| 263 | |
| 264 | switch (nb->device_id) { |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 265 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 266 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 267 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 268 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 269 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 270 | dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; |
| 271 | break; |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 272 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 273 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 274 | case PCI_DEVICE_ID_INTEL_82Q965: |
Warren Turkal | 5329195 | 2010-09-03 09:32:17 +0000 | [diff] [blame] | 275 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 276 | case PCI_DEVICE_ID_INTEL_82G33: |
| 277 | case PCI_DEVICE_ID_INTEL_82Q33: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 278 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 279 | case PCI_DEVICE_ID_INTEL_32X0: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 280 | case PCI_DEVICE_ID_INTEL_82X4X: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 281 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 282 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Warren Turkal | 5329195 | 2010-09-03 09:32:17 +0000 | [diff] [blame] | 283 | dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; |
| 284 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 285 | break; |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 286 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 287 | case PCI_DEVICE_ID_INTEL_82810_DC: |
| 288 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 289 | case PCI_DEVICE_ID_INTEL_82865: |
| 290 | printf("This northbridge does not have DMIBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 291 | return 1; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 292 | case PCI_DEVICE_ID_INTEL_82X58: |
Warren Turkal | 3235eea | 2010-09-03 09:31:13 +0000 | [diff] [blame] | 293 | dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; |
| 294 | break; |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 295 | case PCI_DEVICE_ID_INTEL_CORE_0TH_GEN: |
| 296 | /* DMIBAR is called DMIRCBAR in Nehalem */ |
| 297 | dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; /* 31:12 */ |
| 298 | dmi_registers = nehalem_dmi_registers; |
| 299 | size = ARRAY_SIZE(nehalem_dmi_registers); |
| 300 | break; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 301 | case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: |
| 302 | dmibar_phys = pci_read_long(nb, 0x68); |
| 303 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 304 | dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 305 | dmi_registers = westmere_dmi_registers; |
| 306 | size = ARRAY_SIZE(westmere_dmi_registers); |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 307 | break; |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 308 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 309 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 310 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 311 | dmi_registers = sandybridge_dmi_registers; |
| 312 | size = ARRAY_SIZE(sandybridge_dmi_registers); |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 313 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: /* pretty printing not implemented yet */ |
| 314 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 315 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 316 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
| 317 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: |
| 318 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: |
| 319 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 320 | dmibar_phys = pci_read_long(nb, 0x68); |
| 321 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 322 | dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 323 | break; |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 324 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 325 | case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 326 | dmi_registers = haswell_ult_dmi_registers; |
| 327 | size = ARRAY_SIZE(haswell_ult_dmi_registers); |
| 328 | dmibar_phys = pci_read_long(nb, 0x68); |
| 329 | dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; |
| 330 | dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ |
| 331 | break; |
| 332 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 333 | default: |
| 334 | printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); |
| 335 | return 1; |
| 336 | } |
| 337 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 338 | dmibar = map_physical(dmibar_phys, size); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 339 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 340 | if (dmibar == NULL) { |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 341 | perror("Error mapping DMIBAR"); |
| 342 | exit(1); |
| 343 | } |
| 344 | |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 345 | printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys); |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 346 | if (dmi_registers != NULL) { |
| 347 | for (i = 0; i < size; i++) { |
| 348 | switch (dmi_registers[i].size) { |
| 349 | case 4: |
| 350 | printf("dmibase+0x%04x: 0x%08x (%s)\n", |
| 351 | dmi_registers[i].addr, |
| 352 | *(uint32_t *)(dmibar+dmi_registers[i].addr), |
| 353 | dmi_registers[i].name); |
| 354 | break; |
| 355 | case 2: |
| 356 | printf("dmibase+0x%04x: 0x%04x (%s)\n", |
| 357 | dmi_registers[i].addr, |
| 358 | *(uint16_t *)(dmibar+dmi_registers[i].addr), |
| 359 | dmi_registers[i].name); |
| 360 | break; |
| 361 | case 1: |
| 362 | printf("dmibase+0x%04x: 0x%02x (%s)\n", |
| 363 | dmi_registers[i].addr, |
| 364 | *(uint8_t *)(dmibar+dmi_registers[i].addr), |
| 365 | dmi_registers[i].name); |
| 366 | break; |
| 367 | } |
| 368 | } |
| 369 | } else { |
| 370 | for (i = 0; i < size; i += 4) { |
| 371 | if (*(uint32_t *)(dmibar + i)) |
| 372 | printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); |
| 373 | } |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 376 | unmap_physical((void *)dmibar, size); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | /* |
| 381 | * PCIe MMIO configuration space |
| 382 | */ |
| 383 | int print_pciexbar(struct pci_dev *nb) |
| 384 | { |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 385 | uint64_t pciexbar_reg; |
| 386 | uint64_t pciexbar_phys; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 387 | volatile uint8_t *pciexbar; |
| 388 | int max_busses, devbase, i; |
| 389 | int bus, dev, fn; |
| 390 | |
| 391 | printf("========= PCIEXBAR ========\n\n"); |
| 392 | |
| 393 | switch (nb->device_id) { |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 394 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 395 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 396 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 397 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 398 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 399 | pciexbar_reg = pci_read_long(nb, 0x48); |
| 400 | break; |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 401 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 402 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 403 | case PCI_DEVICE_ID_INTEL_82Q965: |
| 404 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 405 | case PCI_DEVICE_ID_INTEL_82G33: |
| 406 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 407 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 408 | case PCI_DEVICE_ID_INTEL_32X0: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 409 | case PCI_DEVICE_ID_INTEL_82X4X: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 410 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 411 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 412 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 413 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
| 414 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
| 415 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
| 416 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 417 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 418 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
| 419 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: |
| 420 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: |
| 421 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 422 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 423 | case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 424 | pciexbar_reg = pci_read_long(nb, 0x60); |
| 425 | pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; |
| 426 | break; |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 427 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 428 | case PCI_DEVICE_ID_INTEL_82810_DC: |
| 429 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 430 | case PCI_DEVICE_ID_INTEL_82865: |
| 431 | printf("Error: This northbridge does not have PCIEXBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 432 | return 1; |
| 433 | default: |
| 434 | printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); |
| 435 | return 1; |
| 436 | } |
| 437 | |
| 438 | if (!(pciexbar_reg & (1 << 0))) { |
| 439 | printf("PCIEXBAR register is disabled.\n"); |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | switch ((pciexbar_reg >> 1) & 3) { |
| 444 | case 0: // 256MB |
Paul Menzel | 17c05f2 | 2013-04-03 10:00:33 +0200 | [diff] [blame] | 445 | pciexbar_phys = pciexbar_reg & (0xffULL << 28); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 446 | max_busses = 256; |
| 447 | break; |
| 448 | case 1: // 128M |
Paul Menzel | 17c05f2 | 2013-04-03 10:00:33 +0200 | [diff] [blame] | 449 | pciexbar_phys = pciexbar_reg & (0x1ffULL << 27); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 450 | max_busses = 128; |
| 451 | break; |
| 452 | case 2: // 64M |
Paul Menzel | 17c05f2 | 2013-04-03 10:00:33 +0200 | [diff] [blame] | 453 | pciexbar_phys = pciexbar_reg & (0x3ffULL << 26); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 454 | max_busses = 64; |
| 455 | break; |
| 456 | default: // RSVD |
| 457 | printf("Undefined address base. Bailing out.\n"); |
| 458 | return 1; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 459 | } |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 460 | |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 461 | printf("PCIEXBAR: 0x%08" PRIx64 "\n", pciexbar_phys); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 462 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 463 | pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024)); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 464 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 465 | if (pciexbar == NULL) { |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 466 | perror("Error mapping PCIEXBAR"); |
| 467 | exit(1); |
| 468 | } |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 469 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 470 | for (bus = 0; bus < max_busses; bus++) { |
| 471 | for (dev = 0; dev < 32; dev++) { |
| 472 | for (fn = 0; fn < 8; fn++) { |
| 473 | devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024); |
| 474 | |
| 475 | if (*(uint16_t *)(pciexbar + devbase) == 0xffff) |
| 476 | continue; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 477 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 478 | /* This is a heuristics. Anyone got a better check? */ |
| 479 | if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) && |
| 480 | (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) { |
| 481 | #if DEBUG |
| 482 | printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn); |
| 483 | #endif |
| 484 | continue; |
| 485 | } |
| 486 | |
| 487 | printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn); |
| 488 | for (i = 0; i < 4096; i++) { |
| 489 | if((i % 0x10) == 0) |
| 490 | printf("\n%04x:", i); |
| 491 | printf(" %02x", *(pciexbar+devbase+i)); |
| 492 | } |
| 493 | printf("\n"); |
| 494 | } |
| 495 | } |
| 496 | } |
| 497 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 498 | unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024)); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 499 | |
| 500 | return 0; |
| 501 | } |