Add support for the Intel Atom D400/500- and N400-series integrated
northbridge. Also add support for the very similar Q963/965 northbridge.
Tested:
D510: confirmed working, with MCHBAR enable code
Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
Untested:
D410/D525/N400: should be the same northbridge
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 771a28f..10b79e4 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -40,10 +40,13 @@
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_PM965:
+ case PCI_DEVICE_ID_INTEL_Q965:
case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
+ case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break;
@@ -94,10 +97,13 @@
dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_PM965:
+ case PCI_DEVICE_ID_INTEL_Q965:
case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
+ case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
break;
@@ -149,10 +155,13 @@
pciexbar_reg = pci_read_long(nb, 0x48);
break;
case PCI_DEVICE_ID_INTEL_PM965:
+ case PCI_DEVICE_ID_INTEL_Q965:
case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
+ case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;