inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflow
When building inteltool with Clang, it warns about the following.
$ clang --version
Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
Target: i386-pc-linux-gnu
Thread model: posix
$ CC=clang make
[…]
clang -O2 -g -Wall -W -c -o pcie.o pcie.c
pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
pciexbar_phys = pciexbar_reg & (0xff << 28);
~~~~ ^ ~~
pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
pciexbar_phys = pciexbar_reg & (0x1ff << 27);
~~~~~ ^ ~~
pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
pciexbar_phys = pciexbar_reg & (0x3ff << 26);
~~~~~ ^ ~~
3 warnings generated.
[…]
Specifying the length by using the suffix `0xffULL` fixes these issues
as now enough bits are available.
These issues were introduced in commit 1162f25a [1].
commit 1162f25a49e8f39822123d664cda10fef466b351
Author: Stefan Reinauer <stepan@coresystems.de>
Date: Thu Dec 4 15:18:20 2008 +0000
Patch to util/inteltool:
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO
[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39822123d664cda10fef466b351
Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3015
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 752d7b0..8c95257 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -294,15 +294,15 @@
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
- pciexbar_phys = pciexbar_reg & (0xff << 28);
+ pciexbar_phys = pciexbar_reg & (0xffULL << 28);
max_busses = 256;
break;
case 1: // 128M
- pciexbar_phys = pciexbar_reg & (0x1ff << 27);
+ pciexbar_phys = pciexbar_reg & (0x1ffULL << 27);
max_busses = 128;
break;
case 2: // 64M
- pciexbar_phys = pciexbar_reg & (0x3ff << 26);
+ pciexbar_phys = pciexbar_reg & (0x3ffULL << 26);
max_busses = 64;
break;
default: // RSVD