Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 1 | chip northbridge/intel/sandybridge |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 2 | # IGD Displays |
Nico Huber | b0b25c8 | 2020-03-21 20:35:12 +0100 | [diff] [blame] | 3 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 4 | |
| 5 | # Enable DisplayPort Hotplug with 6ms pulse |
| 6 | register "gpu_dp_d_hotplug" = "0x06" |
| 7 | |
| 8 | # Enable Panel as LVDS and configure power delays |
Angel Pons | dc0c081 | 2020-09-02 19:17:30 +0200 | [diff] [blame] | 9 | register "gpu_panel_port_select" = "PANEL_PORT_LVDS" |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 10 | register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms |
| 11 | register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms |
| 12 | register "gpu_panel_power_down_delay" = "150" # T3: 15ms |
| 13 | register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms |
| 14 | register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms |
| 15 | |
Matt DeVillier | eaea9c9 | 2018-12-31 15:07:42 -0600 | [diff] [blame] | 16 | # Set backlight PWM values |
| 17 | register "gpu_cpu_backlight" = "0x000001e8" |
| 18 | register "gpu_pch_backlight" = "0x03d00000" |
| 19 | |
Vladimir Serbinenko | 0a07c5c | 2016-02-10 03:01:37 +0100 | [diff] [blame] | 20 | register "max_mem_clock_mhz" = "666" |
| 21 | |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 22 | device domain 0 on |
Stefan Reinauer | 56c7dc7 | 2012-05-15 12:36:57 -0700 | [diff] [blame] | 23 | subsystemid 0x1ae0 0xc000 inherit |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame^] | 24 | device ref host_bridge on end # host bridge |
| 25 | device ref igd on end # vga controller |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 26 | |
| 27 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 28 | # GPI routing |
| 29 | # 0 No effect (default) |
| 30 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 31 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 32 | register "alt_gp_smi_en" = "0x0002" |
| 33 | register "gpi1_routing" = "1" |
| 34 | register "gpi7_routing" = "2" |
| 35 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 36 | register "sata_port_map" = "0x1" |
| 37 | |
| 38 | # EC range is 0xa00-0xa3f |
| 39 | register "gen1_dec" = "0x003c0a01" |
| 40 | register "gen2_dec" = "0x003c0b01" |
Arthur Heymans | 6beaef9 | 2019-06-16 23:29:23 +0200 | [diff] [blame] | 41 | register "gen3_dec" = "0x00fc1601" |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 42 | |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame^] | 43 | device ref mei1 on end # Management Engine Interface 1 |
| 44 | device ref mei2 off end # Management Engine Interface 2 |
| 45 | device ref me_ide_r off end # Management Engine IDE-R |
| 46 | device ref me_kt off end # Management Engine KT |
| 47 | device ref gbe off end # Intel Gigabit Ethernet |
| 48 | device ref ehci2 on end # USB2 EHCI #2 |
| 49 | device ref hda on end # High Definition Audio |
| 50 | device ref pcie_rp1 on end # PCIe Port #1 (WLAN) |
| 51 | device ref pcie_rp2 off end # PCIe Port #2 |
| 52 | device ref pcie_rp3 off end # PCIe Port #3 |
| 53 | device ref pcie_rp4 on end # PCIe Port #4 (LAN) |
| 54 | device ref pcie_rp5 off end # PCIe Port #5 |
| 55 | device ref pcie_rp6 off end # PCIe Port #6 |
| 56 | device ref pcie_rp7 off end # PCIe Port #7 |
| 57 | device ref pcie_rp8 off end # PCIe Port #8 |
| 58 | device ref ehci1 on end # USB2 EHCI #1 |
| 59 | device ref pci_bridge off end # PCI bridge |
| 60 | device ref lpc on # LPC bridge |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 61 | chip superio/smsc/mec1308 |
| 62 | device pnp 2e.1 on # PM1 |
| 63 | io 0x60 = 0xb00 |
| 64 | end |
| 65 | device pnp 2e.2 off end # EC1 |
| 66 | device pnp 2e.3 off end # EC2 |
| 67 | device pnp 2e.4 off end # UART |
| 68 | device pnp 2e.7 on # KBC |
| 69 | irq 0x70 = 1 |
| 70 | end |
| 71 | device pnp 2e.8 on # EC0 |
| 72 | io 0x60 = 0x62 |
| 73 | end |
| 74 | device pnp 2e.9 on # MBX |
| 75 | io 0x60 = 0xa00 |
| 76 | end |
| 77 | end |
| 78 | chip ec/smsc/mec1308 |
| 79 | register "mailbox_port" = "0xa00" |
| 80 | device pnp ff.1 off end |
| 81 | end |
Matt DeVillier | 3044af7 | 2018-08-01 13:05:14 -0500 | [diff] [blame] | 82 | chip drivers/pc80/tpm |
| 83 | device pnp 0c31.0 on end |
| 84 | end |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 85 | end |
Arthur Heymans | b5df65a | 2022-11-12 14:51:49 +0100 | [diff] [blame^] | 86 | device ref sata1 on end # SATA Controller 1 |
| 87 | device ref smbus on end # SMBus |
| 88 | device ref sata2 off end # SATA Controller 2 |
| 89 | device ref thermal on end # Thermal |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 90 | end |
| 91 | end |
| 92 | end |