Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Matt DeVillier | 8f42472 | 2019-11-27 22:55:43 -0600 | [diff] [blame] | 3 | # IGD Displays |
| 4 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 5 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 6 | # Deep Sx states |
| 7 | register "deep_s3_enable_ac" = "0" |
| 8 | register "deep_s3_enable_dc" = "1" |
| 9 | register "deep_s5_enable_ac" = "1" |
| 10 | register "deep_s5_enable_dc" = "1" |
Furquan Shaikh | 9076b7b | 2018-02-05 12:08:57 -0800 | [diff] [blame] | 11 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 12 | |
| 13 | # GPE configuration |
| 14 | # Note that GPE events called out in ASL code rely on this |
| 15 | # route. i.e. If this route changes then the affected GPE |
| 16 | # offset bits also need to be changed. |
| 17 | register "gpe0_dw0" = "GPP_B" |
| 18 | register "gpe0_dw1" = "GPP_D" |
| 19 | register "gpe0_dw2" = "GPP_E" |
| 20 | |
| 21 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 22 | register "gen1_dec" = "0x00fc0801" |
| 23 | register "gen2_dec" = "0x000c0201" |
| 24 | # EC memory map range is 0x900-0x9ff |
| 25 | register "gen3_dec" = "0x00fc0901" |
| 26 | |
Frank Wu | 2a67c37 | 2018-03-30 14:24:05 +0800 | [diff] [blame] | 27 | # Enable DPTF |
| 28 | register "dptf_enable" = "1" |
| 29 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 30 | # Enable S0ix |
| 31 | register "s0ix_enable" = "1" |
| 32 | |
| 33 | # FSP Configuration |
| 34 | register "ProbelessTrace" = "0" |
| 35 | register "EnableLan" = "0" |
Kane Chen | cb8123a | 2018-01-22 16:24:10 +0800 | [diff] [blame] | 36 | register "EnableSata" = "0" |
| 37 | register "SataSalpSupport" = "0" |
Furquan Shaikh | ac9fd16 | 2017-12-17 03:19:18 -0800 | [diff] [blame] | 38 | register "SataMode" = "0" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 39 | register "EnableAzalia" = "1" |
| 40 | register "DspEnable" = "1" |
| 41 | register "IoBufferOwnership" = "3" |
| 42 | register "EnableTraceHub" = "0" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 43 | register "SsicPortEnable" = "0" |
| 44 | register "SmbusEnable" = "1" |
| 45 | register "Cio2Enable" = "0" |
| 46 | register "SaImguEnable" = "0" |
| 47 | register "ScsEmmcEnabled" = "1" |
| 48 | register "ScsEmmcHs400Enabled" = "1" |
| 49 | register "ScsSdCardEnabled" = "0" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 50 | register "PttSwitch" = "0" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 51 | register "SkipExtGfxScan" = "1" |
| 52 | register "Device4Enable" = "1" |
| 53 | register "HeciEnabled" = "0" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 54 | register "SaGv" = "3" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 55 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 56 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 57 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 58 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 59 | register "PmTimerDisabled" = "1" |
| 60 | |
Shelley Chen | 60c44e2 | 2018-08-01 10:41:27 -0700 | [diff] [blame] | 61 | # Intersil VR c-state issue workaround |
| 62 | # send VR mailbox command for IA/GT/SA rails |
| 63 | register "IslVrCmd" = "2" |
| 64 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 65 | register "pirqa_routing" = "PCH_IRQ11" |
| 66 | register "pirqb_routing" = "PCH_IRQ10" |
| 67 | register "pirqc_routing" = "PCH_IRQ11" |
| 68 | register "pirqd_routing" = "PCH_IRQ11" |
| 69 | register "pirqe_routing" = "PCH_IRQ11" |
| 70 | register "pirqf_routing" = "PCH_IRQ11" |
| 71 | register "pirqg_routing" = "PCH_IRQ11" |
| 72 | register "pirqh_routing" = "PCH_IRQ11" |
| 73 | |
| 74 | # VR Settings Configuration for 4 Domains |
| 75 | #+----------------+-------+-------+-------+-------+ |
| 76 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 77 | #+----------------+-------+-------+-------+-------+ |
| 78 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 79 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
| 80 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 81 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 82 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 83 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 84 | #| ImonOffset | 0 | 0 | 0 | 0 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 85 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 86 | #| AcLoadline | 11 | 2.4 | 3.1 | 3.1 | |
| 87 | #| DcLoadline | 10 | 2.46 | 3.1 | 3.1 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 88 | #+----------------+-------+-------+-------+-------+ |
| 89 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 90 | .vr_config_enable = 1, |
| 91 | .psi1threshold = VR_CFG_AMP(20), |
| 92 | .psi2threshold = VR_CFG_AMP(2), |
| 93 | .psi3threshold = VR_CFG_AMP(1), |
| 94 | .psi3enable = 1, |
| 95 | .psi4enable = 1, |
| 96 | .imon_slope = 0x0, |
| 97 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 98 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 99 | .ac_loadline = 1100, |
| 100 | .dc_loadline = 1000, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 101 | }" |
| 102 | |
| 103 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 104 | .vr_config_enable = 1, |
| 105 | .psi1threshold = VR_CFG_AMP(20), |
| 106 | .psi2threshold = VR_CFG_AMP(2), |
| 107 | .psi3threshold = VR_CFG_AMP(1), |
| 108 | .psi3enable = 1, |
| 109 | .psi4enable = 1, |
| 110 | .imon_slope = 0x0, |
| 111 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 112 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 113 | .ac_loadline = 240, |
| 114 | .dc_loadline = 246, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 115 | }" |
| 116 | |
| 117 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 118 | .vr_config_enable = 1, |
| 119 | .psi1threshold = VR_CFG_AMP(20), |
| 120 | .psi2threshold = VR_CFG_AMP(2), |
| 121 | .psi3threshold = VR_CFG_AMP(1), |
| 122 | .psi3enable = 1, |
| 123 | .psi4enable = 1, |
| 124 | .imon_slope = 0x0, |
| 125 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 126 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 127 | .ac_loadline = 310, |
| 128 | .dc_loadline = 310, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 129 | }" |
| 130 | |
| 131 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 132 | .vr_config_enable = 1, |
| 133 | .psi1threshold = VR_CFG_AMP(20), |
| 134 | .psi2threshold = VR_CFG_AMP(2), |
| 135 | .psi3threshold = VR_CFG_AMP(1), |
| 136 | .psi3enable = 1, |
| 137 | .psi4enable = 1, |
| 138 | .imon_slope = 0x0, |
| 139 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 140 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 141 | .ac_loadline = 310, |
| 142 | .dc_loadline = 310, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 143 | }" |
| 144 | |
| 145 | # Root port 4 (x1) |
| 146 | # PcieRpEnable: Enable root port |
| 147 | # PcieRpClkReqSupport: Enable CLKREQ# |
| 148 | # PcieRpClkReqNumber: Uses SRCCLKREQ1# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 149 | # PcieRpClkSrcNumber: Uses 1 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 150 | # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting |
| 151 | # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism |
| 152 | register "PcieRpEnable[3]" = "1" |
| 153 | register "PcieRpClkReqSupport[3]" = "1" |
| 154 | register "PcieRpClkReqNumber[3]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 155 | register "PcieRpClkSrcNumber[3]" = "1" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 156 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 157 | register "PcieRpLtrEnable[3]" = "1" |
| 158 | |
| 159 | # Root port 5 (x4) |
| 160 | # PcieRpEnable: Enable root port |
| 161 | # PcieRpClkReqSupport: Enable CLKREQ# |
| 162 | # PcieRpClkReqNumber: Uses SRCCLKREQ3# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 163 | # PcieRpClkSrcNumber: Uses 3 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 164 | # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting |
| 165 | # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism |
| 166 | register "PcieRpEnable[4]" = "1" |
| 167 | register "PcieRpClkReqSupport[4]" = "1" |
| 168 | register "PcieRpClkReqNumber[4]" = "3" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 169 | register "PcieRpClkSrcNumber[4]" = "3" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 170 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 171 | register "PcieRpLtrEnable[4]" = "1" |
| 172 | |
| 173 | # Root port 9 (x2) |
| 174 | # PcieRpEnable: Enable root port |
| 175 | # PcieRpClkReqSupport: Enable CLKREQ# |
| 176 | # PcieRpClkReqNumber: Uses SRCCLKREQ2# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 177 | # PcieRpClkSrcNumber: Uses 2 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 178 | # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting |
| 179 | # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism |
| 180 | register "PcieRpEnable[8]" = "1" |
| 181 | register "PcieRpClkReqSupport[8]" = "1" |
| 182 | register "PcieRpClkReqNumber[8]" = "2" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 183 | register "PcieRpClkSrcNumber[8]" = "2" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 184 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 185 | register "PcieRpLtrEnable[8]" = "1" |
| 186 | |
| 187 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0 |
| 188 | register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 |
| 189 | register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port |
| 190 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader |
| 191 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi |
| 192 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera |
| 193 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera |
| 194 | |
| 195 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0 |
| 196 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 |
| 197 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port |
| 198 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader |
| 199 | |
| 200 | # Touchscreen |
| 201 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| 202 | |
| 203 | # Trackpad |
| 204 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
| 205 | |
| 206 | # Pen |
| 207 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" |
| 208 | |
| 209 | # Audio |
| 210 | register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" |
| 211 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 212 | # Intel Common SoC Config |
| 213 | #+-------------------+---------------------------+ |
| 214 | #| Field | Value | |
| 215 | #+-------------------+---------------------------+ |
| 216 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 217 | #| GSPI0 | cr50 TPM. Early init is | |
| 218 | #| | required to set up a BAR | |
| 219 | #| | for TPM communication | |
| 220 | #| | before memory is up | |
| 221 | #| I2C0 | Touchscreen | |
| 222 | #| I2C1 | Trackpad | |
| 223 | #| I2C2 | Pen | |
| 224 | #| I2C3 | Audio | |
Subrata Banik | c077b22 | 2019-08-01 10:50:35 +0530 | [diff] [blame] | 225 | #| pch_thermal_trip | PCH Trip Temperature | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 226 | #+-------------------+---------------------------+ |
| 227 | register "common_soc_config" = "{ |
| 228 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 229 | .gspi[0] = { |
| 230 | .speed_mhz = 1, |
| 231 | .early_init = 1, |
| 232 | }, |
| 233 | .i2c[0] = { |
| 234 | .speed = I2C_SPEED_FAST, |
| 235 | .speed_config[0] = { |
| 236 | .speed = I2C_SPEED_FAST, |
| 237 | .scl_lcnt = 185, |
| 238 | .scl_hcnt = 90, |
| 239 | .sda_hold = 36, |
| 240 | }, |
| 241 | }, |
| 242 | .i2c[1] = { |
| 243 | .speed = I2C_SPEED_FAST, |
| 244 | .speed_config[0] = { |
| 245 | .speed = I2C_SPEED_FAST, |
| 246 | .scl_lcnt = 185, |
| 247 | .scl_hcnt = 90, |
| 248 | .sda_hold = 36, |
| 249 | }, |
| 250 | .early_init = 1, |
| 251 | }, |
| 252 | .i2c[2] = { |
| 253 | .speed = I2C_SPEED_FAST, |
| 254 | .speed_config[0] = { |
| 255 | .speed = I2C_SPEED_FAST, |
| 256 | .scl_lcnt = 185, |
| 257 | .scl_hcnt = 100, |
| 258 | .sda_hold = 36, |
| 259 | }, |
| 260 | }, |
| 261 | .i2c[3] = { |
| 262 | .speed = I2C_SPEED_FAST, |
| 263 | .speed_config[0] = { |
| 264 | .speed = I2C_SPEED_FAST, |
| 265 | .scl_lcnt = 195, |
| 266 | .scl_hcnt = 90, |
| 267 | .sda_hold = 36, |
| 268 | }, |
| 269 | }, |
Subrata Banik | c077b22 | 2019-08-01 10:50:35 +0530 | [diff] [blame] | 270 | .pch_thermal_trip = 75, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 271 | }" |
| 272 | |
| 273 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 274 | register "SerialIoDevMode" = "{ |
| 275 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 276 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 277 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 278 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 279 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 280 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 281 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
Shelley Chen | 715cb40 | 2018-10-26 14:07:16 -0700 | [diff] [blame] | 282 | [PchSerialIoIndexSpi1] = PchSerialIoPci, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 283 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 284 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 285 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 286 | }" |
| 287 | |
| 288 | register "speed_shift_enable" = "1" |
| 289 | |
John Su | 31ff06a | 2018-06-13 14:28:46 +0800 | [diff] [blame] | 290 | register "tcc_offset" = "3" # TCC of 97C |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame^] | 291 | register "power_limits_config" = "{ |
| 292 | .psys_pmax = 101, |
| 293 | }" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 294 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 295 | device cpu_cluster 0 on |
| 296 | device lapic 0 on end |
| 297 | end |
| 298 | device domain 0 on |
| 299 | device pci 00.0 on end # Host Bridge |
| 300 | device pci 02.0 on end # Integrated Graphics Device |
| 301 | device pci 14.0 on end # USB xHCI |
Shelley Chen | e1d5fac | 2018-06-21 14:03:00 -0700 | [diff] [blame] | 302 | device pci 14.1 on end # USB xDCI (OTG) |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 303 | device pci 14.2 on end # Thermal Subsystem |
Crystal Lin | e099b30 | 2018-02-26 17:04:06 +0800 | [diff] [blame] | 304 | device pci 15.0 on |
| 305 | chip drivers/i2c/generic |
| 306 | register "hid" = ""ELAN0001"" |
| 307 | register "desc" = ""ELAN Touchscreen"" |
| 308 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
| 309 | register "probed" = "1" |
| 310 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" |
| 311 | register "reset_delay_ms" = "20" |
Shelley Chen | 51be4ed | 2018-04-20 11:16:15 -0700 | [diff] [blame] | 312 | register "reset_off_delay_ms" = "2" |
Shelley Chen | 6a0eafe | 2018-03-14 09:55:11 -0700 | [diff] [blame] | 313 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" |
Shelley Chen | e3be9c0 | 2018-05-30 20:15:18 -0700 | [diff] [blame] | 314 | register "enable_delay_ms" = "5" |
Shelley Chen | 51be4ed | 2018-04-20 11:16:15 -0700 | [diff] [blame] | 315 | register "enable_off_delay_ms" = "100" |
Crystal Lin | e099b30 | 2018-02-26 17:04:06 +0800 | [diff] [blame] | 316 | register "has_power_resource" = "1" |
Shelley Chen | 51be4ed | 2018-04-20 11:16:15 -0700 | [diff] [blame] | 317 | register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" |
| 318 | register "stop_off_delay_ms" = "2" |
Crystal Lin | e099b30 | 2018-02-26 17:04:06 +0800 | [diff] [blame] | 319 | device i2c 10 on end |
| 320 | end |
Ren Kuo | d48a3a3 | 2018-10-31 10:22:39 +0800 | [diff] [blame] | 321 | chip drivers/i2c/generic |
| 322 | register "hid" = ""RAYD0001"" |
| 323 | register "desc" = ""Raydium Touchscreen"" |
| 324 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
| 325 | register "probed" = "1" |
| 326 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" |
| 327 | register "reset_delay_ms" = "1" |
| 328 | register "reset_off_delay_ms" = "2" |
| 329 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" |
| 330 | register "enable_delay_ms" = "10" |
| 331 | register "enable_off_delay_ms" = "100" |
| 332 | register "has_power_resource" = "1" |
| 333 | register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" |
| 334 | register "stop_delay_ms" = "20" |
| 335 | register "stop_off_delay_ms" = "2" |
| 336 | device i2c 39 on end |
| 337 | end |
Ivy Jian | aeb50d2 | 2018-04-30 11:38:00 +0800 | [diff] [blame] | 338 | chip drivers/i2c/hid |
| 339 | register "generic.hid" = ""SYTS7817"" |
| 340 | register "generic.desc" = ""Synaptics Touchscreen"" |
| 341 | register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
| 342 | register "generic.probed" = "1" |
| 343 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" |
| 344 | register "generic.enable_delay_ms" = "45" |
| 345 | register "generic.has_power_resource" = "1" |
| 346 | register "generic.disable_gpio_export_in_crs" = "1" |
| 347 | register "hid_desc_reg_offset" = "0x20" |
| 348 | device i2c 20 on end |
| 349 | end |
Crystal Lin | e547bfc | 2018-11-21 15:58:20 +0800 | [diff] [blame] | 350 | chip drivers/i2c/hid |
| 351 | register "generic.hid" = ""GTCH7503"" |
| 352 | register "generic.desc" = ""G2TOUCH Touchscreen"" |
| 353 | register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
| 354 | register "generic.probed" = "1" |
| 355 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" |
| 356 | register "generic.reset_delay_ms" = "50" |
| 357 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" |
| 358 | register "generic.enable_delay_ms" = "1" |
| 359 | register "generic.has_power_resource" = "1" |
| 360 | register "generic.disable_gpio_export_in_crs" = "1" |
| 361 | register "hid_desc_reg_offset" = "0x01" |
| 362 | device i2c 40 on end |
| 363 | end |
Crystal Lin | e099b30 | 2018-02-26 17:04:06 +0800 | [diff] [blame] | 364 | end # I2C #0 |
van_chen | b94b2c7 | 2018-01-05 15:45:03 +0800 | [diff] [blame] | 365 | device pci 15.1 on |
| 366 | chip drivers/i2c/generic |
| 367 | register "hid" = ""ELAN0000"" |
| 368 | register "desc" = ""ELAN Touchpad"" |
| 369 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" |
Van Chen | f56e71b | 2018-01-19 15:16:19 +0800 | [diff] [blame] | 370 | register "wake" = "GPE0_DW2_16" |
van_chen | b94b2c7 | 2018-01-05 15:45:03 +0800 | [diff] [blame] | 371 | device i2c 15 on end |
| 372 | end |
ivy_jian | b7641e8 | 2018-04-30 09:53:11 +0800 | [diff] [blame] | 373 | chip drivers/i2c/hid |
| 374 | register "generic.hid" = ""PNP0C50"" |
| 375 | register "generic.desc" = ""Synaptics Touchpad"" |
| 376 | register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" |
| 377 | register "generic.wake" = "GPE0_DW2_16" |
| 378 | register "generic.probed" = "1" |
| 379 | register "hid_desc_reg_offset" = "0x20" |
| 380 | device i2c 0x2c on end |
| 381 | end |
van_chen | b94b2c7 | 2018-01-05 15:45:03 +0800 | [diff] [blame] | 382 | end # I2C #1 |
jasper lee | f393d43 | 2018-03-05 20:01:42 +0800 | [diff] [blame] | 383 | device pci 15.2 on |
| 384 | chip drivers/i2c/hid |
| 385 | register "generic.hid" = ""WCOM005C"" |
| 386 | register "generic.desc" = ""WCOM Digitizer"" |
| 387 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" |
| 388 | register "generic.probed" = "1" |
| 389 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" |
| 390 | register "generic.reset_delay_ms" = "20" |
| 391 | register "generic.has_power_resource" = "1" |
| 392 | register "generic.disable_gpio_export_in_crs" = "1" |
Shelley Chen | 4e0b47a | 2018-03-14 11:19:24 -0700 | [diff] [blame] | 393 | register "generic.wake" = "GPE0_DW2_01" |
jasper lee | f393d43 | 2018-03-05 20:01:42 +0800 | [diff] [blame] | 394 | register "hid_desc_reg_offset" = "0x1" |
| 395 | device i2c 0x9 on end |
| 396 | end |
Shelley Chen | 4e0b47a | 2018-03-14 11:19:24 -0700 | [diff] [blame] | 397 | chip drivers/generic/gpio_keys |
| 398 | register "name" = ""PENH"" |
Shelley Chen | 5430d01 | 2018-05-02 15:49:41 -0700 | [diff] [blame] | 399 | register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_E8)" |
| 400 | register "key.dev_name" = ""INST"" |
Shelley Chen | 4e0b47a | 2018-03-14 11:19:24 -0700 | [diff] [blame] | 401 | register "key.linux_code" = "SW_PEN_INSERTED" |
| 402 | register "key.linux_input_type" = "EV_SW" |
Shelley Chen | 5430d01 | 2018-05-02 15:49:41 -0700 | [diff] [blame] | 403 | register "key.label" = ""pen_insert"" |
Shelley Chen | 4e0b47a | 2018-03-14 11:19:24 -0700 | [diff] [blame] | 404 | device generic 0 on end |
| 405 | end |
jasper lee | f393d43 | 2018-03-05 20:01:42 +0800 | [diff] [blame] | 406 | end # I2C #2 |
Gaggery Tsai | ff9005b | 2017-12-13 16:47:57 +0800 | [diff] [blame] | 407 | device pci 15.3 on |
| 408 | chip drivers/generic/max98357a |
Aamir Bohra | a1c82c5 | 2020-03-16 18:57:48 +0530 | [diff] [blame] | 409 | register "hid" = ""MX98357A"" |
Gaggery Tsai | ff9005b | 2017-12-13 16:47:57 +0800 | [diff] [blame] | 410 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" |
| 411 | register "sdmode_delay" = "5" |
| 412 | device generic 0 on end |
| 413 | end |
| 414 | chip drivers/i2c/da7219 |
| 415 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" |
| 416 | register "btn_cfg" = "50" |
| 417 | register "mic_det_thr" = "500" |
| 418 | register "jack_ins_deb" = "20" |
| 419 | register "jack_det_rate" = ""32ms_64ms"" |
| 420 | register "jack_rem_deb" = "1" |
| 421 | register "a_d_btn_thr" = "0xa" |
| 422 | register "d_b_btn_thr" = "0x16" |
| 423 | register "b_c_btn_thr" = "0x21" |
| 424 | register "c_mic_btn_thr" = "0x3e" |
| 425 | register "btn_avg" = "4" |
| 426 | register "adc_1bit_rpt" = "1" |
| 427 | register "micbias_lvl" = "2600" |
| 428 | register "mic_amp_in_sel" = ""diff"" |
| 429 | device i2c 1A on end |
| 430 | end |
| 431 | end # I2C #3 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 432 | device pci 16.0 on end # Management Engine Interface 1 |
| 433 | device pci 16.1 off end # Management Engine Interface 2 |
| 434 | device pci 16.2 off end # Management Engine IDE-R |
| 435 | device pci 16.3 off end # Management Engine KT Redirection |
| 436 | device pci 16.4 off end # Management Engine Interface 3 |
Kane Chen | cb8123a | 2018-01-22 16:24:10 +0800 | [diff] [blame] | 437 | device pci 17.0 off end # SATA |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 438 | device pci 19.0 on end # UART #2 |
| 439 | device pci 19.1 off end # I2C #5 |
| 440 | device pci 19.2 off end # I2C #4 |
| 441 | device pci 1c.0 on end # PCI Express Port 1 |
| 442 | device pci 1c.1 off end # PCI Express Port 2 |
| 443 | device pci 1c.2 off end # PCI Express Port 3 |
| 444 | device pci 1c.3 on |
| 445 | chip drivers/intel/wifi |
Furquan Shaikh | 9076b7b | 2018-02-05 12:08:57 -0800 | [diff] [blame] | 446 | register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 447 | device pci 00.0 on end |
| 448 | end |
| 449 | end # PCI Express Port 4 |
| 450 | device pci 1c.4 on end # PCI Express Port 5 |
| 451 | device pci 1c.5 off end # PCI Express Port 6 |
| 452 | device pci 1c.6 off end # PCI Express Port 7 |
| 453 | device pci 1c.7 off end # PCI Express Port 8 |
| 454 | device pci 1d.0 on end # PCI Express Port 9 |
| 455 | device pci 1d.1 off end # PCI Express Port 10 |
| 456 | device pci 1d.2 off end # PCI Express Port 11 |
| 457 | device pci 1d.3 off end # PCI Express Port 12 |
| 458 | device pci 1e.0 on end # UART #0 |
| 459 | device pci 1e.1 off end # UART #1 |
| 460 | device pci 1e.2 on |
| 461 | chip drivers/spi/acpi |
| 462 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 463 | register "compat_string" = ""google,cr50"" |
| 464 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 465 | device spi 0 on end |
| 466 | end |
| 467 | end # GSPI #0 |
Shelley Chen | 715cb40 | 2018-10-26 14:07:16 -0700 | [diff] [blame] | 468 | device pci 1e.3 on |
| 469 | chip drivers/spi/acpi |
| 470 | register "name" = ""CRFP"" |
| 471 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 472 | register "uid" = "1" |
| 473 | register "compat_string" = ""google,cros-ec-spi"" |
Shelley Chen | c4ce11b | 2018-11-27 17:19:53 -0800 | [diff] [blame] | 474 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B0_IRQ)" |
| 475 | register "wake" = "GPE0_DW0_01" # GPP_B1 |
Shelley Chen | 715cb40 | 2018-10-26 14:07:16 -0700 | [diff] [blame] | 476 | device spi 0 on end |
| 477 | end # FPMCU |
| 478 | end # GSPI #1 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 479 | device pci 1e.4 on end # eMMC |
| 480 | device pci 1e.5 off end # SDIO |
| 481 | device pci 1e.6 off end # SDCard |
| 482 | device pci 1f.0 on |
| 483 | chip ec/google/chromeec |
| 484 | device pnp 0c09.0 on end |
| 485 | end |
| 486 | end # LPC Interface |
| 487 | device pci 1f.1 on end # P2SB |
| 488 | device pci 1f.2 on end # Power Management Controller |
| 489 | device pci 1f.3 on end # Intel HDA |
| 490 | device pci 1f.4 on end # SMBus |
| 491 | device pci 1f.5 on end # PCH SPI |
| 492 | device pci 1f.6 off end # GbE |
| 493 | end |
| 494 | end |