soc/intel/skylake: Make use of common thermal code for SKL
This patch ensures skylake soc is using common thermal code
from intel common block.
TEST=Build and boot soraka
Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 7c11ea1..3d37eda 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -219,6 +219,7 @@
#| I2C1 | Trackpad |
#| I2C2 | Pen |
#| I2C3 | Audio |
+ #| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@@ -263,6 +264,7 @@
.sda_hold = 36,
},
},
+ .pch_thermal_trip = 75,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
@@ -285,9 +287,6 @@
register "tcc_offset" = "3" # TCC of 97C
register "psys_pmax" = "101"
- # PCH Trip Temperature in degree C
- register "pch_trip_temp" = "75"
-
device cpu_cluster 0 on
device lapic 0 on end
end