Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "1" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
Furquan Shaikh | 9076b7b | 2018-02-05 12:08:57 -0800 | [diff] [blame] | 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_B" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | # EC memory map range is 0x900-0x9ff |
| 22 | register "gen3_dec" = "0x00fc0901" |
| 23 | |
| 24 | # Enable S0ix |
| 25 | register "s0ix_enable" = "1" |
| 26 | |
| 27 | # FSP Configuration |
| 28 | register "ProbelessTrace" = "0" |
| 29 | register "EnableLan" = "0" |
Kane Chen | cb8123a | 2018-01-22 16:24:10 +0800 | [diff] [blame] | 30 | register "EnableSata" = "0" |
| 31 | register "SataSalpSupport" = "0" |
Furquan Shaikh | ac9fd16 | 2017-12-17 03:19:18 -0800 | [diff] [blame] | 32 | register "SataMode" = "0" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 33 | register "EnableAzalia" = "1" |
| 34 | register "DspEnable" = "1" |
| 35 | register "IoBufferOwnership" = "3" |
| 36 | register "EnableTraceHub" = "0" |
| 37 | register "XdciEnable" = "0" |
| 38 | register "SsicPortEnable" = "0" |
| 39 | register "SmbusEnable" = "1" |
| 40 | register "Cio2Enable" = "0" |
| 41 | register "SaImguEnable" = "0" |
| 42 | register "ScsEmmcEnabled" = "1" |
| 43 | register "ScsEmmcHs400Enabled" = "1" |
| 44 | register "ScsSdCardEnabled" = "0" |
| 45 | register "IshEnable" = "0" |
| 46 | register "PttSwitch" = "0" |
| 47 | register "InternalGfx" = "1" |
| 48 | register "SkipExtGfxScan" = "1" |
| 49 | register "Device4Enable" = "1" |
| 50 | register "HeciEnabled" = "0" |
| 51 | register "FspSkipMpInit" = "1" |
| 52 | register "SaGv" = "3" |
| 53 | register "SerialIrqConfigSirqEnable" = "1" |
| 54 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 55 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 56 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 57 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 58 | register "PmTimerDisabled" = "1" |
| 59 | |
| 60 | register "pirqa_routing" = "PCH_IRQ11" |
| 61 | register "pirqb_routing" = "PCH_IRQ10" |
| 62 | register "pirqc_routing" = "PCH_IRQ11" |
| 63 | register "pirqd_routing" = "PCH_IRQ11" |
| 64 | register "pirqe_routing" = "PCH_IRQ11" |
| 65 | register "pirqf_routing" = "PCH_IRQ11" |
| 66 | register "pirqg_routing" = "PCH_IRQ11" |
| 67 | register "pirqh_routing" = "PCH_IRQ11" |
| 68 | |
| 69 | # VR Settings Configuration for 4 Domains |
| 70 | #+----------------+-------+-------+-------+-------+ |
| 71 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 72 | #+----------------+-------+-------+-------+-------+ |
| 73 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 74 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
| 75 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 76 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 77 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 78 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 79 | #| ImonOffset | 0 | 0 | 0 | 0 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 80 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 81 | #| AcLoadline | 11 | 2.4 | 3.1 | 3.1 | |
| 82 | #| DcLoadline | 10 | 2.46 | 3.1 | 3.1 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 83 | #+----------------+-------+-------+-------+-------+ |
| 84 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 85 | .vr_config_enable = 1, |
| 86 | .psi1threshold = VR_CFG_AMP(20), |
| 87 | .psi2threshold = VR_CFG_AMP(2), |
| 88 | .psi3threshold = VR_CFG_AMP(1), |
| 89 | .psi3enable = 1, |
| 90 | .psi4enable = 1, |
| 91 | .imon_slope = 0x0, |
| 92 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 93 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 94 | .ac_loadline = 1100, |
| 95 | .dc_loadline = 1000, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 96 | }" |
| 97 | |
| 98 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 99 | .vr_config_enable = 1, |
| 100 | .psi1threshold = VR_CFG_AMP(20), |
| 101 | .psi2threshold = VR_CFG_AMP(2), |
| 102 | .psi3threshold = VR_CFG_AMP(1), |
| 103 | .psi3enable = 1, |
| 104 | .psi4enable = 1, |
| 105 | .imon_slope = 0x0, |
| 106 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 107 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 108 | .ac_loadline = 240, |
| 109 | .dc_loadline = 246, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 110 | }" |
| 111 | |
| 112 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 113 | .vr_config_enable = 1, |
| 114 | .psi1threshold = VR_CFG_AMP(20), |
| 115 | .psi2threshold = VR_CFG_AMP(2), |
| 116 | .psi3threshold = VR_CFG_AMP(1), |
| 117 | .psi3enable = 1, |
| 118 | .psi4enable = 1, |
| 119 | .imon_slope = 0x0, |
| 120 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 121 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 122 | .ac_loadline = 310, |
| 123 | .dc_loadline = 310, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 124 | }" |
| 125 | |
| 126 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 127 | .vr_config_enable = 1, |
| 128 | .psi1threshold = VR_CFG_AMP(20), |
| 129 | .psi2threshold = VR_CFG_AMP(2), |
| 130 | .psi3threshold = VR_CFG_AMP(1), |
| 131 | .psi3enable = 1, |
| 132 | .psi4enable = 1, |
| 133 | .imon_slope = 0x0, |
| 134 | .imon_offset = 0x0, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 135 | .voltage_limit = 1520, |
Gaggery Tsai | 2a81fed | 2018-02-05 13:47:39 +0800 | [diff] [blame] | 136 | .ac_loadline = 310, |
| 137 | .dc_loadline = 310, |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 138 | }" |
| 139 | |
| 140 | # Root port 4 (x1) |
| 141 | # PcieRpEnable: Enable root port |
| 142 | # PcieRpClkReqSupport: Enable CLKREQ# |
| 143 | # PcieRpClkReqNumber: Uses SRCCLKREQ1# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 144 | # PcieRpClkSrcNumber: Uses 1 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 145 | # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting |
| 146 | # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism |
| 147 | register "PcieRpEnable[3]" = "1" |
| 148 | register "PcieRpClkReqSupport[3]" = "1" |
| 149 | register "PcieRpClkReqNumber[3]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 150 | register "PcieRpClkSrcNumber[3]" = "1" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 151 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 152 | register "PcieRpLtrEnable[3]" = "1" |
| 153 | |
| 154 | # Root port 5 (x4) |
| 155 | # PcieRpEnable: Enable root port |
| 156 | # PcieRpClkReqSupport: Enable CLKREQ# |
| 157 | # PcieRpClkReqNumber: Uses SRCCLKREQ3# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 158 | # PcieRpClkSrcNumber: Uses 3 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 159 | # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting |
| 160 | # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism |
| 161 | register "PcieRpEnable[4]" = "1" |
| 162 | register "PcieRpClkReqSupport[4]" = "1" |
| 163 | register "PcieRpClkReqNumber[4]" = "3" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 164 | register "PcieRpClkSrcNumber[4]" = "3" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 165 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 166 | register "PcieRpLtrEnable[4]" = "1" |
| 167 | |
| 168 | # Root port 9 (x2) |
| 169 | # PcieRpEnable: Enable root port |
| 170 | # PcieRpClkReqSupport: Enable CLKREQ# |
| 171 | # PcieRpClkReqNumber: Uses SRCCLKREQ2# |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 172 | # PcieRpClkSrcNumber: Uses 2 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 173 | # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting |
| 174 | # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism |
| 175 | register "PcieRpEnable[8]" = "1" |
| 176 | register "PcieRpClkReqSupport[8]" = "1" |
| 177 | register "PcieRpClkReqNumber[8]" = "2" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 178 | register "PcieRpClkSrcNumber[8]" = "2" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 179 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 180 | register "PcieRpLtrEnable[8]" = "1" |
| 181 | |
| 182 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0 |
| 183 | register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1 |
| 184 | register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port |
| 185 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader |
| 186 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi |
| 187 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera |
| 188 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera |
| 189 | |
| 190 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0 |
| 191 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 |
| 192 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port |
| 193 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader |
| 194 | |
| 195 | # Touchscreen |
| 196 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| 197 | |
| 198 | # Trackpad |
| 199 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
| 200 | |
| 201 | # Pen |
| 202 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" |
| 203 | |
| 204 | # Audio |
| 205 | register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" |
| 206 | |
| 207 | # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM |
| 208 | # communication before memory is up. |
| 209 | register "gspi[0]" = "{ |
| 210 | .speed_mhz = 1, |
| 211 | .early_init = 1, |
| 212 | }" |
| 213 | |
| 214 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 215 | register "SerialIoDevMode" = "{ |
| 216 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 217 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 218 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 219 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 220 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 221 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 222 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
| 223 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 224 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 225 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 226 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 227 | }" |
| 228 | |
| 229 | register "speed_shift_enable" = "1" |
| 230 | |
| 231 | register "tcc_offset" = "10" # TCC of 90C |
Gaggery Tsai | cb304c1 | 2018-02-07 17:17:05 +0800 | [diff] [blame] | 232 | register "psys_pmax" = "101" |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 233 | |
| 234 | # Lock Down |
| 235 | register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" |
| 236 | |
Furquan Shaikh | 39d3021 | 2018-03-01 18:08:06 -0800 | [diff] [blame] | 237 | # PCH Trip Temperature in degree C |
| 238 | register "pch_trip_temp" = "75" |
| 239 | |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 240 | device cpu_cluster 0 on |
| 241 | device lapic 0 on end |
| 242 | end |
| 243 | device domain 0 on |
| 244 | device pci 00.0 on end # Host Bridge |
| 245 | device pci 02.0 on end # Integrated Graphics Device |
| 246 | device pci 14.0 on end # USB xHCI |
| 247 | device pci 14.1 off end # USB xDCI (OTG) |
| 248 | device pci 14.2 on end # Thermal Subsystem |
Crystal Lin | e099b30 | 2018-02-26 17:04:06 +0800 | [diff] [blame] | 249 | device pci 15.0 on |
| 250 | chip drivers/i2c/generic |
| 251 | register "hid" = ""ELAN0001"" |
| 252 | register "desc" = ""ELAN Touchscreen"" |
| 253 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
| 254 | register "probed" = "1" |
| 255 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" |
| 256 | register "reset_delay_ms" = "20" |
| 257 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" |
| 258 | register "enable_delay_ms" = "1" |
| 259 | register "has_power_resource" = "1" |
| 260 | device i2c 10 on end |
| 261 | end |
| 262 | end # I2C #0 |
van_chen | b94b2c7 | 2018-01-05 15:45:03 +0800 | [diff] [blame] | 263 | device pci 15.1 on |
| 264 | chip drivers/i2c/generic |
| 265 | register "hid" = ""ELAN0000"" |
| 266 | register "desc" = ""ELAN Touchpad"" |
| 267 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" |
Van Chen | f56e71b | 2018-01-19 15:16:19 +0800 | [diff] [blame] | 268 | register "wake" = "GPE0_DW2_16" |
van_chen | b94b2c7 | 2018-01-05 15:45:03 +0800 | [diff] [blame] | 269 | device i2c 15 on end |
| 270 | end |
| 271 | end # I2C #1 |
jasper lee | f393d43 | 2018-03-05 20:01:42 +0800 | [diff] [blame^] | 272 | device pci 15.2 on |
| 273 | chip drivers/i2c/hid |
| 274 | register "generic.hid" = ""WCOM005C"" |
| 275 | register "generic.desc" = ""WCOM Digitizer"" |
| 276 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" |
| 277 | register "generic.probed" = "1" |
| 278 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" |
| 279 | register "generic.reset_delay_ms" = "20" |
| 280 | register "generic.has_power_resource" = "1" |
| 281 | register "generic.disable_gpio_export_in_crs" = "1" |
| 282 | register "hid_desc_reg_offset" = "0x1" |
| 283 | device i2c 0x9 on end |
| 284 | end |
| 285 | end # I2C #2 |
Gaggery Tsai | ff9005b | 2017-12-13 16:47:57 +0800 | [diff] [blame] | 286 | device pci 15.3 on |
| 287 | chip drivers/generic/max98357a |
| 288 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" |
| 289 | register "sdmode_delay" = "5" |
| 290 | device generic 0 on end |
| 291 | end |
| 292 | chip drivers/i2c/da7219 |
| 293 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" |
| 294 | register "btn_cfg" = "50" |
| 295 | register "mic_det_thr" = "500" |
| 296 | register "jack_ins_deb" = "20" |
| 297 | register "jack_det_rate" = ""32ms_64ms"" |
| 298 | register "jack_rem_deb" = "1" |
| 299 | register "a_d_btn_thr" = "0xa" |
| 300 | register "d_b_btn_thr" = "0x16" |
| 301 | register "b_c_btn_thr" = "0x21" |
| 302 | register "c_mic_btn_thr" = "0x3e" |
| 303 | register "btn_avg" = "4" |
| 304 | register "adc_1bit_rpt" = "1" |
| 305 | register "micbias_lvl" = "2600" |
| 306 | register "mic_amp_in_sel" = ""diff"" |
| 307 | device i2c 1A on end |
| 308 | end |
| 309 | end # I2C #3 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 310 | device pci 16.0 on end # Management Engine Interface 1 |
| 311 | device pci 16.1 off end # Management Engine Interface 2 |
| 312 | device pci 16.2 off end # Management Engine IDE-R |
| 313 | device pci 16.3 off end # Management Engine KT Redirection |
| 314 | device pci 16.4 off end # Management Engine Interface 3 |
Kane Chen | cb8123a | 2018-01-22 16:24:10 +0800 | [diff] [blame] | 315 | device pci 17.0 off end # SATA |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 316 | device pci 19.0 on end # UART #2 |
| 317 | device pci 19.1 off end # I2C #5 |
| 318 | device pci 19.2 off end # I2C #4 |
| 319 | device pci 1c.0 on end # PCI Express Port 1 |
| 320 | device pci 1c.1 off end # PCI Express Port 2 |
| 321 | device pci 1c.2 off end # PCI Express Port 3 |
| 322 | device pci 1c.3 on |
| 323 | chip drivers/intel/wifi |
Furquan Shaikh | 9076b7b | 2018-02-05 12:08:57 -0800 | [diff] [blame] | 324 | register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 |
Furquan Shaikh | 903472c | 2017-12-04 17:41:44 -0800 | [diff] [blame] | 325 | device pci 00.0 on end |
| 326 | end |
| 327 | end # PCI Express Port 4 |
| 328 | device pci 1c.4 on end # PCI Express Port 5 |
| 329 | device pci 1c.5 off end # PCI Express Port 6 |
| 330 | device pci 1c.6 off end # PCI Express Port 7 |
| 331 | device pci 1c.7 off end # PCI Express Port 8 |
| 332 | device pci 1d.0 on end # PCI Express Port 9 |
| 333 | device pci 1d.1 off end # PCI Express Port 10 |
| 334 | device pci 1d.2 off end # PCI Express Port 11 |
| 335 | device pci 1d.3 off end # PCI Express Port 12 |
| 336 | device pci 1e.0 on end # UART #0 |
| 337 | device pci 1e.1 off end # UART #1 |
| 338 | device pci 1e.2 on |
| 339 | chip drivers/spi/acpi |
| 340 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 341 | register "compat_string" = ""google,cr50"" |
| 342 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 343 | device spi 0 on end |
| 344 | end |
| 345 | end # GSPI #0 |
| 346 | device pci 1e.3 off end # GSPI #1 |
| 347 | device pci 1e.4 on end # eMMC |
| 348 | device pci 1e.5 off end # SDIO |
| 349 | device pci 1e.6 off end # SDCard |
| 350 | device pci 1f.0 on |
| 351 | chip ec/google/chromeec |
| 352 | device pnp 0c09.0 on end |
| 353 | end |
| 354 | end # LPC Interface |
| 355 | device pci 1f.1 on end # P2SB |
| 356 | device pci 1f.2 on end # Power Management Controller |
| 357 | device pci 1f.3 on end # Intel HDA |
| 358 | device pci 1f.4 on end # SMBus |
| 359 | device pci 1f.5 on end # PCH SPI |
| 360 | device pci 1f.6 off end # GbE |
| 361 | end |
| 362 | end |