Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 9 | #include <delay.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 10 | #include "chip.h" |
Angel Pons | 2178b72 | 2020-05-31 00:55:35 +0200 | [diff] [blame] | 11 | #include "iobp.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 12 | #include "pch.h" |
| 13 | |
Angel Pons | be6ad1a | 2020-10-30 13:55:23 +0100 | [diff] [blame] | 14 | #if CONFIG(INTEL_LYNXPOINT_LP) |
| 15 | #define SATA_PORT_MASK 0x0f |
| 16 | #else |
| 17 | #define SATA_PORT_MASK 0x3f |
| 18 | #endif |
| 19 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | static inline u32 sir_read(struct device *dev, int idx) |
| 21 | { |
| 22 | pci_write_config32(dev, SATA_SIRI, idx); |
| 23 | return pci_read_config32(dev, SATA_SIRD); |
| 24 | } |
| 25 | |
| 26 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 27 | { |
| 28 | pci_write_config32(dev, SATA_SIRI, idx); |
| 29 | pci_write_config32(dev, SATA_SIRD, value); |
| 30 | } |
| 31 | |
Angel Pons | d00af4f | 2020-10-30 12:56:02 +0100 | [diff] [blame] | 32 | static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) |
| 33 | { |
| 34 | pci_write_config32(dev, SATA_SIRI, idx); |
| 35 | |
| 36 | const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; |
| 37 | pci_write_config32(dev, SATA_SIRD, value | set); |
| 38 | } |
| 39 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | static void sata_init(struct device *dev) |
| 41 | { |
| 42 | u32 reg32; |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 43 | |
| 44 | u32 *abar; |
| 45 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 46 | /* Get the chip configuration */ |
Angel Pons | efebedd | 2021-09-08 16:16:58 +0200 | [diff] [blame] | 47 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 48 | |
| 49 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 50 | |
| 51 | if (config == NULL) { |
| 52 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
| 53 | return; |
| 54 | } |
| 55 | |
| 56 | /* SATA configuration */ |
| 57 | |
Angel Pons | 1b85692 | 2020-10-30 15:30:48 +0100 | [diff] [blame] | 58 | /* Enable memory space decoding for ABAR */ |
| 59 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 60 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 61 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 63 | /* Set Interrupt Line */ |
| 64 | /* Interrupt Pin is set by D31IP.PIP */ |
Angel Pons | 93859e3 | 2020-11-02 12:08:50 +0100 | [diff] [blame] | 65 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 66 | |
Angel Pons | 93859e3 | 2020-11-02 12:08:50 +0100 | [diff] [blame] | 67 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); |
| 68 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 69 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 70 | /* for AHCI, Port Enable is managed in memory mapped space */ |
Angel Pons | be6ad1a | 2020-10-30 13:55:23 +0100 | [diff] [blame] | 71 | pci_update_config16(dev, 0x92, ~SATA_PORT_MASK, 0x8000 | config->sata_port_map); |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 72 | udelay(2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 74 | /* Setup register 98h */ |
Angel Pons | 9b629ad | 2020-11-02 12:13:23 +0100 | [diff] [blame] | 75 | reg32 = pci_read_config32(dev, 0x98); |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 76 | reg32 |= 1 << 19; /* BWG step 6 */ |
| 77 | reg32 |= 1 << 22; /* BWG step 5 */ |
| 78 | reg32 &= ~(0x3f << 7); |
| 79 | reg32 |= 0x04 << 7; /* BWG step 7 */ |
| 80 | reg32 |= 1 << 20; /* BWG step 8 */ |
| 81 | reg32 &= ~(0x03 << 5); |
| 82 | reg32 |= 1 << 5; /* BWG step 9 */ |
| 83 | reg32 |= 1 << 18; /* BWG step 10 */ |
| 84 | reg32 |= 1 << 29; /* BWG step 11 */ |
| 85 | if (pch_is_lp()) { |
| 86 | reg32 &= ~((1 << 31) | (1 << 30)); |
| 87 | reg32 |= 1 << 23; |
| 88 | reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 89 | } |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 90 | pci_write_config32(dev, 0x98, reg32); |
| 91 | |
| 92 | /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ |
| 93 | pci_write_config16(dev, 0x9c, 1 << 5); |
| 94 | |
| 95 | /* SATA Initialization register */ |
| 96 | reg32 = 0x183; |
Angel Pons | be6ad1a | 2020-10-30 13:55:23 +0100 | [diff] [blame] | 97 | reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24; |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame] | 98 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 99 | pci_write_config32(dev, 0x94, reg32); |
| 100 | |
| 101 | /* Initialize AHCI memory-mapped space */ |
| 102 | abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 103 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
| 104 | /* CAP (HBA Capabilities) : enable power management */ |
| 105 | reg32 = read32(abar + 0x00); |
| 106 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 107 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
| 108 | if (pch_is_lp()) |
| 109 | reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY |
| 110 | write32(abar + 0x00, reg32); |
| 111 | /* PI (Ports implemented) */ |
| 112 | write32(abar + 0x03, config->sata_port_map); |
| 113 | (void)read32(abar + 0x03); /* Read back 1 */ |
| 114 | (void)read32(abar + 0x03); /* Read back 2 */ |
| 115 | /* CAP2 (HBA Capabilities Extended)*/ |
| 116 | reg32 = read32(abar + 0x09); |
| 117 | /* Enable DEVSLP */ |
| 118 | if (pch_is_lp()) { |
| 119 | if (config->sata_devslp_disable) |
| 120 | reg32 &= ~(1 << 3); |
| 121 | else |
| 122 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 123 | } else { |
| 124 | reg32 &= ~0x00000002; |
| 125 | } |
| 126 | write32(abar + 0x09, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 127 | |
| 128 | /* Set Gen3 Transmitter settings if needed */ |
| 129 | if (config->sata_port0_gen3_tx) |
| 130 | pch_iobp_update(SATA_IOBP_SP0G3IR, 0, |
| 131 | config->sata_port0_gen3_tx); |
| 132 | |
| 133 | if (config->sata_port1_gen3_tx) |
| 134 | pch_iobp_update(SATA_IOBP_SP1G3IR, 0, |
| 135 | config->sata_port1_gen3_tx); |
| 136 | |
Shawn Nematbakhsh | 2875227 | 2013-08-13 10:45:21 -0700 | [diff] [blame] | 137 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 138 | if (config->sata_port0_gen3_dtle) { |
| 139 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 140 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 141 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 142 | << SATA_DTLE_DATA_SHIFT); |
| 143 | |
| 144 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 145 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 146 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 147 | << SATA_DTLE_EDGE_SHIFT); |
| 148 | } |
| 149 | |
| 150 | if (config->sata_port1_gen3_dtle) { |
| 151 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 152 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 153 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 154 | << SATA_DTLE_DATA_SHIFT); |
| 155 | |
| 156 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 157 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 158 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 159 | << SATA_DTLE_EDGE_SHIFT); |
| 160 | } |
| 161 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 162 | /* Additional Programming Requirements */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 163 | /* Power Optimizer */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 164 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 165 | /* Step 1 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 166 | if (pch_is_lp()) |
| 167 | sir_write(dev, 0x64, 0x883c9003); |
| 168 | else |
| 169 | sir_write(dev, 0x64, 0x883c9001); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 170 | |
| 171 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
Angel Pons | d00af4f | 2020-10-30 12:56:02 +0100 | [diff] [blame] | 172 | sir_unset_and_set_mask(dev, 0x68, 0xffff, 0x880a); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 173 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 174 | /* Step 3: SIR 60h[3] = 1 */ |
Angel Pons | d00af4f | 2020-10-30 12:56:02 +0100 | [diff] [blame] | 175 | sir_unset_and_set_mask(dev, 0x60, 0, 1 << 3); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 176 | |
| 177 | /* Step 4: SIR 60h[0] = 1 */ |
Angel Pons | d00af4f | 2020-10-30 12:56:02 +0100 | [diff] [blame] | 178 | sir_unset_and_set_mask(dev, 0x60, 0, 1 << 0); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 179 | |
| 180 | /* Step 5: SIR 60h[1] = 1 */ |
Angel Pons | d00af4f | 2020-10-30 12:56:02 +0100 | [diff] [blame] | 181 | sir_unset_and_set_mask(dev, 0x60, 0, 1 << 1); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 182 | |
| 183 | /* Clock Gating */ |
| 184 | sir_write(dev, 0x70, 0x3f00bf1f); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 185 | if (pch_is_lp()) { |
| 186 | sir_write(dev, 0x54, 0xcf000f0f); |
| 187 | sir_write(dev, 0x58, 0x00190000); |
Angel Pons | 9ffb57c | 2020-10-30 13:48:46 +0100 | [diff] [blame] | 188 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 189 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 190 | |
| 191 | reg32 = pci_read_config32(dev, 0x300); |
| 192 | reg32 |= (1 << 17) | (1 << 16); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 193 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 194 | pci_write_config32(dev, 0x300, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 195 | } |
| 196 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 197 | static void sata_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 198 | { |
| 199 | /* Get the chip configuration */ |
Angel Pons | efebedd | 2021-09-08 16:16:58 +0200 | [diff] [blame] | 200 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 201 | |
| 202 | if (!config) |
| 203 | return; |
| 204 | |
| 205 | /* |
| 206 | * Set SATA controller mode early so the resource allocator can |
| 207 | * properly assign IO/Memory resources for the controller. |
| 208 | */ |
Angel Pons | be6ad1a | 2020-10-30 13:55:23 +0100 | [diff] [blame] | 209 | pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 210 | } |
| 211 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 212 | static struct device_operations sata_ops = { |
| 213 | .read_resources = pci_dev_read_resources, |
| 214 | .set_resources = pci_dev_set_resources, |
| 215 | .enable_resources = pci_dev_enable_resources, |
| 216 | .init = sata_init, |
| 217 | .enable = sata_enable, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 218 | .ops_pci = &pci_dev_ops_pci, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 219 | }; |
| 220 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 221 | static const unsigned short pci_device_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 222 | PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE, |
| 223 | PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI, |
| 224 | PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_1, |
| 225 | PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM, |
| 226 | PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45, |
| 227 | PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_2, |
| 228 | PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE, |
| 229 | PCI_DID_INTEL_LPT_H_MOBILE_SATA_AHCI, |
| 230 | PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_1, |
| 231 | PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM, |
| 232 | PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45, |
| 233 | PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2, |
| 234 | PCI_DID_INTEL_LPT_LP_SATA_AHCI, |
| 235 | PCI_DID_INTEL_LPT_LP_SATA_RAID_1, |
| 236 | PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM, |
| 237 | PCI_DID_INTEL_LPT_LP_SATA_RAID_2, |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 238 | 0 |
| 239 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 240 | |
| 241 | static const struct pci_driver pch_sata __pci_driver = { |
| 242 | .ops = &sata_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 243 | .vendor = PCI_VID_INTEL, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 244 | .devices = pci_device_ids, |
| 245 | }; |