Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 26 | #include <delay.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | #include "pch.h" |
| 28 | |
| 29 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 30 | |
| 31 | static inline u32 sir_read(struct device *dev, int idx) |
| 32 | { |
| 33 | pci_write_config32(dev, SATA_SIRI, idx); |
| 34 | return pci_read_config32(dev, SATA_SIRD); |
| 35 | } |
| 36 | |
| 37 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 38 | { |
| 39 | pci_write_config32(dev, SATA_SIRI, idx); |
| 40 | pci_write_config32(dev, SATA_SIRD, value); |
| 41 | } |
| 42 | |
| 43 | static void sata_init(struct device *dev) |
| 44 | { |
| 45 | u32 reg32; |
| 46 | u16 reg16; |
| 47 | /* Get the chip configuration */ |
| 48 | config_t *config = dev->chip_info; |
| 49 | |
| 50 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 51 | |
| 52 | if (config == NULL) { |
| 53 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
| 54 | return; |
| 55 | } |
| 56 | |
| 57 | /* SATA configuration */ |
| 58 | |
| 59 | /* Enable BARs */ |
| 60 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
| 61 | |
| 62 | if (config->ide_legacy_combined) { |
| 63 | printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); |
| 64 | |
| 65 | /* No AHCI: clear AHCI base */ |
| 66 | pci_write_config32(dev, 0x24, 0x00000000); |
| 67 | /* And without AHCI BAR no memory decoding */ |
| 68 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 69 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 70 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 71 | |
| 72 | pci_write_config8(dev, 0x09, 0x80); |
| 73 | |
| 74 | /* Set timings */ |
| 75 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 76 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 77 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 78 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 79 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 80 | |
| 81 | /* Sync DMA */ |
| 82 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); |
| 83 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); |
| 84 | |
| 85 | /* Set IDE I/O Configuration */ |
| 86 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 87 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 88 | |
| 89 | /* Port enable */ |
| 90 | reg16 = pci_read_config16(dev, 0x92); |
| 91 | reg16 &= ~0x3f; |
| 92 | reg16 |= config->sata_port_map; |
| 93 | pci_write_config16(dev, 0x92, reg16); |
| 94 | |
| 95 | /* SATA Initialization register */ |
| 96 | pci_write_config32(dev, 0x94, |
| 97 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 98 | } else if(config->sata_ahci) { |
| 99 | u32 abar; |
| 100 | |
| 101 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
| 102 | |
| 103 | /* Set Interrupt Line */ |
| 104 | /* Interrupt Pin is set by D31IP.PIP */ |
| 105 | pci_write_config8(dev, INTR_LN, 0x0a); |
| 106 | |
| 107 | /* Set timings */ |
| 108 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 109 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 110 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 111 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 112 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 113 | |
| 114 | /* Sync DMA */ |
| 115 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 116 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
| 117 | |
| 118 | /* Set IDE I/O Configuration */ |
| 119 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 120 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 121 | |
| 122 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 123 | reg16 = pci_read_config16(dev, 0x92); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 124 | reg16 &= ~0x3f; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | reg16 |= 0x8000 | config->sata_port_map; |
| 126 | pci_write_config16(dev, 0x92, reg16); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 127 | udelay(2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 128 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 129 | /* Setup register 98h */ |
| 130 | reg32 = pci_read_config16(dev, 0x98); |
| 131 | reg32 |= 1 << 19; /* BWG step 6 */ |
| 132 | reg32 |= 1 << 22; /* BWG step 5 */ |
| 133 | reg32 &= ~(0x3f << 7); |
| 134 | reg32 |= 0x04 << 7; /* BWG step 7 */ |
| 135 | reg32 |= 1 << 20; /* BWG step 8 */ |
| 136 | reg32 &= ~(0x03 << 5); |
| 137 | reg32 |= 1 << 5; /* BWG step 9 */ |
| 138 | reg32 |= 1 << 18; /* BWG step 10 */ |
| 139 | reg32 |= 1 << 29; /* BWG step 11 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame^] | 140 | if (pch_is_lp()) { |
| 141 | reg32 &= ~((1 << 31) | (1 << 30)); |
| 142 | reg32 |= 1 << 23; |
| 143 | reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ |
| 144 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 145 | pci_write_config32(dev, 0x98, reg32); |
| 146 | |
| 147 | /* Setup register 9Ch */ |
| 148 | reg16 = 0; /* Disable alternate ID */ |
| 149 | reg16 = 1 << 5; /* BWG step 12 */ |
| 150 | pci_write_config16(dev, 0x9c, reg16); |
| 151 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 152 | /* SATA Initialization register */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 153 | reg32 = 0x183; |
| 154 | reg32 |= (config->sata_port_map ^ 0x3f) << 24; |
| 155 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 156 | pci_write_config32(dev, 0x94, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 157 | |
| 158 | /* Initialize AHCI memory-mapped space */ |
| 159 | abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 160 | printk(BIOS_DEBUG, "ABAR: %08X\n", abar); |
| 161 | /* CAP (HBA Capabilities) : enable power management */ |
| 162 | reg32 = read32(abar + 0x00); |
| 163 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 164 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame^] | 165 | if (pch_is_lp()) |
| 166 | reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 167 | write32(abar + 0x00, reg32); |
| 168 | /* PI (Ports implemented) */ |
| 169 | write32(abar + 0x0c, config->sata_port_map); |
| 170 | (void) read32(abar + 0x0c); /* Read back 1 */ |
| 171 | (void) read32(abar + 0x0c); /* Read back 2 */ |
| 172 | /* CAP2 (HBA Capabilities Extended)*/ |
| 173 | reg32 = read32(abar + 0x24); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 174 | /* Enable DEVSLP */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame^] | 175 | if (pch_is_lp()) |
| 176 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 177 | else |
| 178 | reg32 &= ~0x00000002; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 179 | write32(abar + 0x24, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 180 | } else { |
| 181 | printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); |
| 182 | |
| 183 | /* No AHCI: clear AHCI base */ |
| 184 | pci_write_config32(dev, 0x24, 0x00000000); |
| 185 | |
| 186 | /* And without AHCI BAR no memory decoding */ |
| 187 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 188 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 189 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 190 | |
| 191 | /* Native mode capable on both primary and secondary (0xa) |
| 192 | * or'ed with enabled (0x50) = 0xf |
| 193 | */ |
| 194 | pci_write_config8(dev, 0x09, 0x8f); |
| 195 | |
| 196 | /* Set Interrupt Line */ |
| 197 | /* Interrupt Pin is set by D31IP.PIP */ |
| 198 | pci_write_config8(dev, INTR_LN, 0xff); |
| 199 | |
| 200 | /* Set timings */ |
| 201 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 202 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 203 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 204 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 205 | IDE_SITRE | IDE_ISP_3_CLOCKS | |
| 206 | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); |
| 207 | |
| 208 | /* Sync DMA */ |
| 209 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); |
| 210 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); |
| 211 | |
| 212 | /* Set IDE I/O Configuration */ |
| 213 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 214 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 215 | |
| 216 | /* Port enable */ |
| 217 | reg16 = pci_read_config16(dev, 0x92); |
| 218 | reg16 &= ~0x3f; |
| 219 | reg16 |= config->sata_port_map; |
| 220 | pci_write_config16(dev, 0x92, reg16); |
| 221 | |
| 222 | /* SATA Initialization register */ |
| 223 | pci_write_config32(dev, 0x94, |
| 224 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 225 | } |
| 226 | |
| 227 | /* Set Gen3 Transmitter settings if needed */ |
| 228 | if (config->sata_port0_gen3_tx) |
| 229 | pch_iobp_update(SATA_IOBP_SP0G3IR, 0, |
| 230 | config->sata_port0_gen3_tx); |
| 231 | |
| 232 | if (config->sata_port1_gen3_tx) |
| 233 | pch_iobp_update(SATA_IOBP_SP1G3IR, 0, |
| 234 | config->sata_port1_gen3_tx); |
| 235 | |
| 236 | /* Additional Programming Requirements */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 237 | /* Power Optimizer */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 238 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 239 | /* Step 1 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame^] | 240 | if (pch_is_lp()) |
| 241 | sir_write(dev, 0x64, 0x883c9003); |
| 242 | else |
| 243 | sir_write(dev, 0x64, 0x883c9001); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 244 | |
| 245 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 246 | reg32 = sir_read(dev, 0x68); |
| 247 | reg32 &= 0xffff0000; |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 248 | reg32 |= 0x880a; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 249 | sir_write(dev, 0x68, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 250 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 251 | /* Step 3: SIR 60h[3] = 1 */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 252 | reg32 = sir_read(dev, 0x60); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 253 | reg32 |= (1 << 3); |
| 254 | sir_write(dev, 0x60, reg32); |
| 255 | |
| 256 | /* Step 4: SIR 60h[0] = 1 */ |
| 257 | reg32 = sir_read(dev, 0x60); |
| 258 | reg32 |= (1 << 0); |
| 259 | sir_write(dev, 0x60, reg32); |
| 260 | |
| 261 | /* Step 5: SIR 60h[1] = 1 */ |
| 262 | reg32 = sir_read(dev, 0x60); |
| 263 | reg32 |= (1 << 1); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 264 | sir_write(dev, 0x60, reg32); |
| 265 | |
| 266 | /* Clock Gating */ |
| 267 | sir_write(dev, 0x70, 0x3f00bf1f); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame^] | 268 | if (pch_is_lp()) { |
| 269 | sir_write(dev, 0x54, 0xcf000f0f); |
| 270 | sir_write(dev, 0x58, 0x00190000); |
| 271 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 272 | |
| 273 | reg32 = pci_read_config32(dev, 0x300); |
| 274 | reg32 |= (1 << 17) | (1 << 16); |
| 275 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
| 276 | pci_write_config32(dev, 0x300, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | static void sata_enable(device_t dev) |
| 280 | { |
| 281 | /* Get the chip configuration */ |
| 282 | config_t *config = dev->chip_info; |
| 283 | u16 map = 0; |
| 284 | |
| 285 | if (!config) |
| 286 | return; |
| 287 | |
| 288 | /* |
| 289 | * Set SATA controller mode early so the resource allocator can |
| 290 | * properly assign IO/Memory resources for the controller. |
| 291 | */ |
| 292 | if (config->sata_ahci) |
| 293 | map = 0x0060; |
| 294 | |
| 295 | map |= (config->sata_port_map ^ 0x3f) << 8; |
| 296 | |
| 297 | pci_write_config16(dev, 0x90, map); |
| 298 | } |
| 299 | |
| 300 | static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 301 | { |
| 302 | if (!vendor || !device) { |
| 303 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 304 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 305 | } else { |
| 306 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 307 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | static struct pci_operations sata_pci_ops = { |
| 312 | .set_subsystem = sata_set_subsystem, |
| 313 | }; |
| 314 | |
| 315 | static struct device_operations sata_ops = { |
| 316 | .read_resources = pci_dev_read_resources, |
| 317 | .set_resources = pci_dev_set_resources, |
| 318 | .enable_resources = pci_dev_enable_resources, |
| 319 | .init = sata_init, |
| 320 | .enable = sata_enable, |
| 321 | .scan_bus = 0, |
| 322 | .ops_pci = &sata_pci_ops, |
| 323 | }; |
| 324 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 325 | static const unsigned short pci_device_ids[] = { |
| 326 | 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ |
| 327 | 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ |
| 328 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ |
| 329 | 0 |
| 330 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 331 | |
| 332 | static const struct pci_driver pch_sata __pci_driver = { |
| 333 | .ops = &sata_ops, |
| 334 | .vendor = PCI_VENDOR_ID_INTEL, |
| 335 | .devices = pci_device_ids, |
| 336 | }; |
| 337 | |