Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 17 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 23 | #include <delay.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame^] | 24 | #include "chip.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | #include "pch.h" |
| 26 | |
| 27 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 28 | |
| 29 | static inline u32 sir_read(struct device *dev, int idx) |
| 30 | { |
| 31 | pci_write_config32(dev, SATA_SIRI, idx); |
| 32 | return pci_read_config32(dev, SATA_SIRD); |
| 33 | } |
| 34 | |
| 35 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 36 | { |
| 37 | pci_write_config32(dev, SATA_SIRI, idx); |
| 38 | pci_write_config32(dev, SATA_SIRD, value); |
| 39 | } |
| 40 | |
| 41 | static void sata_init(struct device *dev) |
| 42 | { |
| 43 | u32 reg32; |
| 44 | u16 reg16; |
| 45 | /* Get the chip configuration */ |
| 46 | config_t *config = dev->chip_info; |
| 47 | |
| 48 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 49 | |
| 50 | if (config == NULL) { |
| 51 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
| 52 | return; |
| 53 | } |
| 54 | |
| 55 | /* SATA configuration */ |
| 56 | |
| 57 | /* Enable BARs */ |
| 58 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
| 59 | |
| 60 | if (config->ide_legacy_combined) { |
| 61 | printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); |
| 62 | |
| 63 | /* No AHCI: clear AHCI base */ |
| 64 | pci_write_config32(dev, 0x24, 0x00000000); |
| 65 | /* And without AHCI BAR no memory decoding */ |
| 66 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 67 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 68 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 69 | |
| 70 | pci_write_config8(dev, 0x09, 0x80); |
| 71 | |
| 72 | /* Set timings */ |
| 73 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 74 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 75 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 76 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 77 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 78 | |
| 79 | /* Sync DMA */ |
| 80 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); |
| 81 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); |
| 82 | |
| 83 | /* Set IDE I/O Configuration */ |
| 84 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 85 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 86 | |
| 87 | /* Port enable */ |
| 88 | reg16 = pci_read_config16(dev, 0x92); |
| 89 | reg16 &= ~0x3f; |
| 90 | reg16 |= config->sata_port_map; |
| 91 | pci_write_config16(dev, 0x92, reg16); |
| 92 | |
| 93 | /* SATA Initialization register */ |
| 94 | pci_write_config32(dev, 0x94, |
| 95 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
Elyes HAOUAS | 70d79a4 | 2016-08-21 18:36:06 +0200 | [diff] [blame] | 96 | } else if (config->sata_ahci) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 97 | u32 *abar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | |
| 99 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
| 100 | |
| 101 | /* Set Interrupt Line */ |
| 102 | /* Interrupt Pin is set by D31IP.PIP */ |
| 103 | pci_write_config8(dev, INTR_LN, 0x0a); |
| 104 | |
| 105 | /* Set timings */ |
| 106 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 107 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 108 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 109 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 110 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 111 | |
| 112 | /* Sync DMA */ |
| 113 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 114 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
| 115 | |
| 116 | /* Set IDE I/O Configuration */ |
| 117 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 118 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 119 | |
| 120 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 121 | reg16 = pci_read_config16(dev, 0x92); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 122 | reg16 &= ~0x3f; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 123 | reg16 |= 0x8000 | config->sata_port_map; |
| 124 | pci_write_config16(dev, 0x92, reg16); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 125 | udelay(2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 127 | /* Setup register 98h */ |
| 128 | reg32 = pci_read_config16(dev, 0x98); |
| 129 | reg32 |= 1 << 19; /* BWG step 6 */ |
| 130 | reg32 |= 1 << 22; /* BWG step 5 */ |
| 131 | reg32 &= ~(0x3f << 7); |
| 132 | reg32 |= 0x04 << 7; /* BWG step 7 */ |
| 133 | reg32 |= 1 << 20; /* BWG step 8 */ |
| 134 | reg32 &= ~(0x03 << 5); |
| 135 | reg32 |= 1 << 5; /* BWG step 9 */ |
| 136 | reg32 |= 1 << 18; /* BWG step 10 */ |
| 137 | reg32 |= 1 << 29; /* BWG step 11 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 138 | if (pch_is_lp()) { |
Ryan Salsamendi | 3f2fe18 | 2017-07-04 13:14:16 -0700 | [diff] [blame] | 139 | reg32 &= ~((1UL << 31) | (1 << 30)); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 140 | reg32 |= 1 << 23; |
| 141 | reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ |
| 142 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 143 | pci_write_config32(dev, 0x98, reg32); |
| 144 | |
| 145 | /* Setup register 9Ch */ |
| 146 | reg16 = 0; /* Disable alternate ID */ |
| 147 | reg16 = 1 << 5; /* BWG step 12 */ |
| 148 | pci_write_config16(dev, 0x9c, reg16); |
| 149 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 150 | /* SATA Initialization register */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 151 | reg32 = 0x183; |
| 152 | reg32 |= (config->sata_port_map ^ 0x3f) << 24; |
| 153 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 154 | pci_write_config32(dev, 0x94, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 155 | |
| 156 | /* Initialize AHCI memory-mapped space */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 157 | abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 158 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 159 | /* CAP (HBA Capabilities) : enable power management */ |
| 160 | reg32 = read32(abar + 0x00); |
| 161 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 162 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 163 | if (pch_is_lp()) |
| 164 | reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 165 | write32(abar + 0x00, reg32); |
| 166 | /* PI (Ports implemented) */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 167 | write32(abar + 0x03, config->sata_port_map); |
| 168 | (void) read32(abar + 0x03); /* Read back 1 */ |
| 169 | (void) read32(abar + 0x03); /* Read back 2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 170 | /* CAP2 (HBA Capabilities Extended)*/ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 171 | reg32 = read32(abar + 0x09); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 172 | /* Enable DEVSLP */ |
Marc Jones | e05cba2 | 2013-10-30 23:56:26 -0600 | [diff] [blame] | 173 | if (pch_is_lp()) { |
| 174 | if (config->sata_devslp_disable) |
| 175 | reg32 &= ~(1 << 3); |
| 176 | else |
| 177 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 178 | } else { |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 179 | reg32 &= ~0x00000002; |
Marc Jones | e05cba2 | 2013-10-30 23:56:26 -0600 | [diff] [blame] | 180 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 181 | write32(abar + 0x09, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 182 | } else { |
| 183 | printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); |
| 184 | |
| 185 | /* No AHCI: clear AHCI base */ |
| 186 | pci_write_config32(dev, 0x24, 0x00000000); |
| 187 | |
| 188 | /* And without AHCI BAR no memory decoding */ |
| 189 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 190 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 191 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 192 | |
| 193 | /* Native mode capable on both primary and secondary (0xa) |
| 194 | * or'ed with enabled (0x50) = 0xf |
| 195 | */ |
| 196 | pci_write_config8(dev, 0x09, 0x8f); |
| 197 | |
| 198 | /* Set Interrupt Line */ |
| 199 | /* Interrupt Pin is set by D31IP.PIP */ |
| 200 | pci_write_config8(dev, INTR_LN, 0xff); |
| 201 | |
| 202 | /* Set timings */ |
| 203 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 204 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 205 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 206 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 207 | IDE_SITRE | IDE_ISP_3_CLOCKS | |
| 208 | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); |
| 209 | |
| 210 | /* Sync DMA */ |
| 211 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); |
| 212 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); |
| 213 | |
| 214 | /* Set IDE I/O Configuration */ |
| 215 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 216 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 217 | |
| 218 | /* Port enable */ |
| 219 | reg16 = pci_read_config16(dev, 0x92); |
| 220 | reg16 &= ~0x3f; |
| 221 | reg16 |= config->sata_port_map; |
| 222 | pci_write_config16(dev, 0x92, reg16); |
| 223 | |
| 224 | /* SATA Initialization register */ |
| 225 | pci_write_config32(dev, 0x94, |
| 226 | ((config->sata_port_map ^ 0x3f) << 24) | 0x183); |
| 227 | } |
| 228 | |
| 229 | /* Set Gen3 Transmitter settings if needed */ |
| 230 | if (config->sata_port0_gen3_tx) |
| 231 | pch_iobp_update(SATA_IOBP_SP0G3IR, 0, |
| 232 | config->sata_port0_gen3_tx); |
| 233 | |
| 234 | if (config->sata_port1_gen3_tx) |
| 235 | pch_iobp_update(SATA_IOBP_SP1G3IR, 0, |
| 236 | config->sata_port1_gen3_tx); |
| 237 | |
Shawn Nematbakhsh | 2875227 | 2013-08-13 10:45:21 -0700 | [diff] [blame] | 238 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 239 | if (config->sata_port0_gen3_dtle) { |
| 240 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 241 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 242 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 243 | << SATA_DTLE_DATA_SHIFT); |
| 244 | |
| 245 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 246 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 247 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 248 | << SATA_DTLE_EDGE_SHIFT); |
| 249 | } |
| 250 | |
| 251 | if (config->sata_port1_gen3_dtle) { |
| 252 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 253 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 254 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 255 | << SATA_DTLE_DATA_SHIFT); |
| 256 | |
| 257 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 258 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 259 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 260 | << SATA_DTLE_EDGE_SHIFT); |
| 261 | } |
| 262 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 263 | /* Additional Programming Requirements */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 264 | /* Power Optimizer */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 265 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 266 | /* Step 1 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 267 | if (pch_is_lp()) |
| 268 | sir_write(dev, 0x64, 0x883c9003); |
| 269 | else |
| 270 | sir_write(dev, 0x64, 0x883c9001); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 271 | |
| 272 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 273 | reg32 = sir_read(dev, 0x68); |
| 274 | reg32 &= 0xffff0000; |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 275 | reg32 |= 0x880a; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 276 | sir_write(dev, 0x68, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 277 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 278 | /* Step 3: SIR 60h[3] = 1 */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 279 | reg32 = sir_read(dev, 0x60); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 280 | reg32 |= (1 << 3); |
| 281 | sir_write(dev, 0x60, reg32); |
| 282 | |
| 283 | /* Step 4: SIR 60h[0] = 1 */ |
| 284 | reg32 = sir_read(dev, 0x60); |
| 285 | reg32 |= (1 << 0); |
| 286 | sir_write(dev, 0x60, reg32); |
| 287 | |
| 288 | /* Step 5: SIR 60h[1] = 1 */ |
| 289 | reg32 = sir_read(dev, 0x60); |
| 290 | reg32 |= (1 << 1); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 291 | sir_write(dev, 0x60, reg32); |
| 292 | |
| 293 | /* Clock Gating */ |
| 294 | sir_write(dev, 0x70, 0x3f00bf1f); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 295 | if (pch_is_lp()) { |
| 296 | sir_write(dev, 0x54, 0xcf000f0f); |
| 297 | sir_write(dev, 0x58, 0x00190000); |
| 298 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 299 | |
| 300 | reg32 = pci_read_config32(dev, 0x300); |
| 301 | reg32 |= (1 << 17) | (1 << 16); |
Ryan Salsamendi | 0d9b360 | 2017-06-30 17:15:57 -0700 | [diff] [blame] | 302 | reg32 |= (1UL << 31) | (1 << 30) | (1 << 29); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 303 | pci_write_config32(dev, 0x300, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 304 | } |
| 305 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 306 | static void sata_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 307 | { |
| 308 | /* Get the chip configuration */ |
| 309 | config_t *config = dev->chip_info; |
| 310 | u16 map = 0; |
| 311 | |
| 312 | if (!config) |
| 313 | return; |
| 314 | |
| 315 | /* |
| 316 | * Set SATA controller mode early so the resource allocator can |
| 317 | * properly assign IO/Memory resources for the controller. |
| 318 | */ |
| 319 | if (config->sata_ahci) |
| 320 | map = 0x0060; |
| 321 | |
| 322 | map |= (config->sata_port_map ^ 0x3f) << 8; |
| 323 | |
| 324 | pci_write_config16(dev, 0x90, map); |
| 325 | } |
| 326 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 327 | static struct pci_operations sata_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 328 | .set_subsystem = pci_dev_set_subsystem, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 329 | }; |
| 330 | |
| 331 | static struct device_operations sata_ops = { |
| 332 | .read_resources = pci_dev_read_resources, |
| 333 | .set_resources = pci_dev_set_resources, |
| 334 | .enable_resources = pci_dev_enable_resources, |
| 335 | .init = sata_init, |
| 336 | .enable = sata_enable, |
| 337 | .scan_bus = 0, |
| 338 | .ops_pci = &sata_pci_ops, |
| 339 | }; |
| 340 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 341 | static const unsigned short pci_device_ids[] = { |
| 342 | 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ |
| 343 | 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ |
| 344 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ |
| 345 | 0 |
| 346 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 347 | |
| 348 | static const struct pci_driver pch_sata __pci_driver = { |
| 349 | .ops = &sata_ops, |
| 350 | .vendor = PCI_VENDOR_ID_INTEL, |
| 351 | .devices = pci_device_ids, |
| 352 | }; |