Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 9 | #include <delay.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 10 | #include "chip.h" |
Angel Pons | 2178b72 | 2020-05-31 00:55:35 +0200 | [diff] [blame] | 11 | #include "iobp.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 12 | #include "pch.h" |
| 13 | |
| 14 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 15 | |
| 16 | static inline u32 sir_read(struct device *dev, int idx) |
| 17 | { |
| 18 | pci_write_config32(dev, SATA_SIRI, idx); |
| 19 | return pci_read_config32(dev, SATA_SIRD); |
| 20 | } |
| 21 | |
| 22 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 23 | { |
| 24 | pci_write_config32(dev, SATA_SIRI, idx); |
| 25 | pci_write_config32(dev, SATA_SIRD, value); |
| 26 | } |
| 27 | |
| 28 | static void sata_init(struct device *dev) |
| 29 | { |
| 30 | u32 reg32; |
| 31 | u16 reg16; |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 32 | |
| 33 | u32 *abar; |
| 34 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | /* Get the chip configuration */ |
| 36 | config_t *config = dev->chip_info; |
| 37 | |
| 38 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 39 | |
| 40 | if (config == NULL) { |
| 41 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
| 42 | return; |
| 43 | } |
| 44 | |
| 45 | /* SATA configuration */ |
| 46 | |
Angel Pons | 1b85692 | 2020-10-30 15:30:48 +0100 | [diff] [blame] | 47 | /* Enable memory space decoding for ABAR */ |
| 48 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 49 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 50 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 52 | /* Set Interrupt Line */ |
| 53 | /* Interrupt Pin is set by D31IP.PIP */ |
| 54 | pci_write_config8(dev, INTR_LN, 0x0a); |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 55 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 56 | /* Set timings */ |
| 57 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 58 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 59 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 60 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 61 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 63 | /* Sync DMA */ |
| 64 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 65 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 67 | /* Set IDE I/O Configuration */ |
| 68 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 69 | pci_write_config32(dev, IDE_CONFIG, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 70 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 71 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 72 | reg16 = pci_read_config16(dev, 0x92); |
| 73 | reg16 &= ~0x3f; |
| 74 | reg16 |= 0x8000 | config->sata_port_map; |
| 75 | pci_write_config16(dev, 0x92, reg16); |
| 76 | udelay(2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 78 | /* Setup register 98h */ |
| 79 | reg32 = pci_read_config16(dev, 0x98); |
| 80 | reg32 |= 1 << 19; /* BWG step 6 */ |
| 81 | reg32 |= 1 << 22; /* BWG step 5 */ |
| 82 | reg32 &= ~(0x3f << 7); |
| 83 | reg32 |= 0x04 << 7; /* BWG step 7 */ |
| 84 | reg32 |= 1 << 20; /* BWG step 8 */ |
| 85 | reg32 &= ~(0x03 << 5); |
| 86 | reg32 |= 1 << 5; /* BWG step 9 */ |
| 87 | reg32 |= 1 << 18; /* BWG step 10 */ |
| 88 | reg32 |= 1 << 29; /* BWG step 11 */ |
| 89 | if (pch_is_lp()) { |
| 90 | reg32 &= ~((1 << 31) | (1 << 30)); |
| 91 | reg32 |= 1 << 23; |
| 92 | reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 93 | } |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 94 | pci_write_config32(dev, 0x98, reg32); |
| 95 | |
| 96 | /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ |
| 97 | pci_write_config16(dev, 0x9c, 1 << 5); |
| 98 | |
| 99 | /* SATA Initialization register */ |
| 100 | reg32 = 0x183; |
| 101 | reg32 |= (config->sata_port_map ^ 0x3f) << 24; |
| 102 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 103 | pci_write_config32(dev, 0x94, reg32); |
| 104 | |
| 105 | /* Initialize AHCI memory-mapped space */ |
| 106 | abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 107 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
| 108 | /* CAP (HBA Capabilities) : enable power management */ |
| 109 | reg32 = read32(abar + 0x00); |
| 110 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 111 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
| 112 | if (pch_is_lp()) |
| 113 | reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY |
| 114 | write32(abar + 0x00, reg32); |
| 115 | /* PI (Ports implemented) */ |
| 116 | write32(abar + 0x03, config->sata_port_map); |
| 117 | (void)read32(abar + 0x03); /* Read back 1 */ |
| 118 | (void)read32(abar + 0x03); /* Read back 2 */ |
| 119 | /* CAP2 (HBA Capabilities Extended)*/ |
| 120 | reg32 = read32(abar + 0x09); |
| 121 | /* Enable DEVSLP */ |
| 122 | if (pch_is_lp()) { |
| 123 | if (config->sata_devslp_disable) |
| 124 | reg32 &= ~(1 << 3); |
| 125 | else |
| 126 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 127 | } else { |
| 128 | reg32 &= ~0x00000002; |
| 129 | } |
| 130 | write32(abar + 0x09, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 131 | |
| 132 | /* Set Gen3 Transmitter settings if needed */ |
| 133 | if (config->sata_port0_gen3_tx) |
| 134 | pch_iobp_update(SATA_IOBP_SP0G3IR, 0, |
| 135 | config->sata_port0_gen3_tx); |
| 136 | |
| 137 | if (config->sata_port1_gen3_tx) |
| 138 | pch_iobp_update(SATA_IOBP_SP1G3IR, 0, |
| 139 | config->sata_port1_gen3_tx); |
| 140 | |
Shawn Nematbakhsh | 2875227 | 2013-08-13 10:45:21 -0700 | [diff] [blame] | 141 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 142 | if (config->sata_port0_gen3_dtle) { |
| 143 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 144 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 145 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 146 | << SATA_DTLE_DATA_SHIFT); |
| 147 | |
| 148 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 149 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 150 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 151 | << SATA_DTLE_EDGE_SHIFT); |
| 152 | } |
| 153 | |
| 154 | if (config->sata_port1_gen3_dtle) { |
| 155 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 156 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 157 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 158 | << SATA_DTLE_DATA_SHIFT); |
| 159 | |
| 160 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 161 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 162 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 163 | << SATA_DTLE_EDGE_SHIFT); |
| 164 | } |
| 165 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 166 | /* Additional Programming Requirements */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 167 | /* Power Optimizer */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 168 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 169 | /* Step 1 */ |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 170 | if (pch_is_lp()) |
| 171 | sir_write(dev, 0x64, 0x883c9003); |
| 172 | else |
| 173 | sir_write(dev, 0x64, 0x883c9001); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 174 | |
| 175 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 176 | reg32 = sir_read(dev, 0x68); |
| 177 | reg32 &= 0xffff0000; |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 178 | reg32 |= 0x880a; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 179 | sir_write(dev, 0x68, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 180 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 181 | /* Step 3: SIR 60h[3] = 1 */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 182 | reg32 = sir_read(dev, 0x60); |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 183 | reg32 |= (1 << 3); |
| 184 | sir_write(dev, 0x60, reg32); |
| 185 | |
| 186 | /* Step 4: SIR 60h[0] = 1 */ |
| 187 | reg32 = sir_read(dev, 0x60); |
| 188 | reg32 |= (1 << 0); |
| 189 | sir_write(dev, 0x60, reg32); |
| 190 | |
| 191 | /* Step 5: SIR 60h[1] = 1 */ |
| 192 | reg32 = sir_read(dev, 0x60); |
| 193 | reg32 |= (1 << 1); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 194 | sir_write(dev, 0x60, reg32); |
| 195 | |
| 196 | /* Clock Gating */ |
| 197 | sir_write(dev, 0x70, 0x3f00bf1f); |
Duncan Laurie | 70f04b4 | 2013-03-08 17:17:33 -0800 | [diff] [blame] | 198 | if (pch_is_lp()) { |
| 199 | sir_write(dev, 0x54, 0xcf000f0f); |
| 200 | sir_write(dev, 0x58, 0x00190000); |
| 201 | } |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 202 | |
| 203 | reg32 = pci_read_config32(dev, 0x300); |
| 204 | reg32 |= (1 << 17) | (1 << 16); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 205 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 206 | pci_write_config32(dev, 0x300, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 207 | } |
| 208 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 209 | static void sata_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 210 | { |
| 211 | /* Get the chip configuration */ |
| 212 | config_t *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 213 | |
| 214 | if (!config) |
| 215 | return; |
| 216 | |
| 217 | /* |
| 218 | * Set SATA controller mode early so the resource allocator can |
| 219 | * properly assign IO/Memory resources for the controller. |
| 220 | */ |
Angel Pons | 8084b38 | 2020-10-30 10:56:31 +0100 | [diff] [blame^] | 221 | pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ 0x3f) << 8); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 222 | } |
| 223 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 224 | static struct device_operations sata_ops = { |
| 225 | .read_resources = pci_dev_read_resources, |
| 226 | .set_resources = pci_dev_set_resources, |
| 227 | .enable_resources = pci_dev_enable_resources, |
| 228 | .init = sata_init, |
| 229 | .enable = sata_enable, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 230 | .ops_pci = &pci_dev_ops_pci, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 231 | }; |
| 232 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 233 | static const unsigned short pci_device_ids[] = { |
| 234 | 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ |
| 235 | 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ |
| 236 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ |
| 237 | 0 |
| 238 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 239 | |
| 240 | static const struct pci_driver pch_sata __pci_driver = { |
| 241 | .ops = &sata_ops, |
| 242 | .vendor = PCI_VENDOR_ID_INTEL, |
| 243 | .devices = pci_device_ids, |
| 244 | }; |