sb/intel/lynxpoint: Drop invalid SATA registers
Code was copy-pasted from older chips and has no effect on Lynxpoint.
Change-Id: I2c789ba48f175b3c9c9643118fc2209c94f24c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index d8eb2a8..6899e81 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -58,22 +58,10 @@
/* Set Interrupt Line */
/* Interrupt Pin is set by D31IP.PIP */
- pci_write_config8(dev, INTR_LN, 0x0a);
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
- IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */
pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map);